Zobrazeno 1 - 10
of 51
pro vyhledávání: '"Ramchan Woo"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:1081-1091
A 36 mm/sup 2/ graphics processor with fixed-point programmable vertex shader is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics applications. The graphics processor contains an ARM-10 compatible 32-bi
Publikováno v:
IEEE Communications Magazine. 43:90-99
A full 3D graphics pipeline is investigated, and optimizations of graphics architecture are assessed for satisfying the performance requirements and overcoming the limited system resources found in mobile terminals. Two mobile 3D graphics processor a
Publikováno v:
IEEE Journal of Solid-State Circuits. 39:1101-1109
A low-power three-dimensional (3-D) rendering engine with two texture units and 29-Mb embedded DRAM is designed and integrated into an LSI for mobile third-generation (3G) multimedia terminals. Bilinear MIPMAP texture-mapped 3-D graphics can be reali
Autor:
Sungwon Shin, Sung-Eun Kim, Sungdae Choi, Hoi-Jun Yoo, Chi-Weon Yoon, Jin-Yong Chung, Kyung-Dong Yoo, Jeong-Ho Woo, In-Cheol Park, Ramchan Woo, Byeong-Gyu Nam, Seong-Jun Song, Ju-Ho Sohn, Young-Don Bae
Publikováno v:
IEEE Journal of Solid-State Circuits. 39:358-367
A 121-mm/sup 2/ graphics LSI is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics and MPEG-4 applications. The LSI contains a RISC processor with a multiply-accumulate unit (MAC), a 3-D rendering engine,
Publikováno v:
IEEE Journal of Solid-State Circuits. 37:1352-1355
A low-power three-dimensional (3-D) rendering engine is implemented as part of a mobile personal digital assistant (PDA) chip. Six-megabit embedded DRAM macros attached to 8-pixel-parallel rendering logic are logically localized with a 3.2-GB/s runti
Autor:
Jin-Yong Jung, Ramchan Woo, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo, Tae-Hum Yang, Se-Jeong Park, Jeong-Su Kim
Publikováno v:
IEEE Journal of Solid-State Circuits. 37:612-623
Recently, the level of realism in PC graphics applications has been approaching that of high-end graphics workstations, necessitating a more sophisticated texture data cache memory to overcome the finite bandwidth of the AGP or PCI bus. This paper pr
Autor:
Hoi-Jun Yoo, Se-Joong Lee, Jeonghoon Kook, In-Cheol Park, Chi-Weon Yoon, Young-Don Bae, Langmin Lee, Ramchan Woo
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:1758-1767
A low-power multimedia processor for mobile applications is presented. An 80-MHz 32-b RISC with enhanced multiplier, two 20-MHz hardware accelerators with 7.125-Mb embedded DRAM for MPEG-4 visual SP@L1 decoding and 3-D graphics processing, 2-kB dual-
Autor:
Katsu Nakamura, Shoji Kawahito, Jerry Lin, Ramchan Woo, Dan McGrath, Johannes Solhusvik, Makoto Ikeda, Jung-Chak Ahn, Jun Ohta, Jan T. Bosiers, Boyd Fowler
Publikováno v:
ISSCC
High speed imaging is one of the fastest growing semiconductor markets. Growth is currently driven by consumer and industrial applications such as HD video, slow motion play-back, machine vision, 3D range capture, and robotics. This forum will presen
Autor:
Koyu Asai, Tadahiro Kuroda, Masayuki Mizuno, Shintaro Yamamichi, Yukihiro Urakawa, Ramchan Woo, Nobukazu Kondo, Jae Dong Kim, Masayuki Miyamoto
Publikováno v:
2008 IEEE Asian Solid-State Circuits Conference.
Up to now, SiP integration is widely used to increase chip integration density as well as flexibility of combination in heterogeneous devices. Emerging integration and stacking technologies such as 3D integration, TSV (Through Silicon Via), die-to-di
Publikováno v:
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..
A fixed-point multimedia coprocessor is designed and integrated into an ARM-10 based mobile graphics processor for portable 2D and 3D multimedia applications. The user-programmable SIMD vertex shader with ARM-10 co-processor architecture realizes adv