Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Ramanan V. Chebiam"'
Autor:
Matthew V. Metz, James S. Clarke, Mauro J. Kobrinsky, J. Bielefeld, Ramanan V. Chebiam, Marius K. Orlowski, Sean W. King, Carl H. Naylor, S. Vyas, John J. Plombon, R. Thapa, Vamseedhara Vemuri, James M. Blackwell, Ye Fan, David J. Michalak, Florian Gstrein, Nicholas C. Strandwitz, Michelle M. Paquette
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
The remarkable advancement of CMOS electronics over the past two decades has been greatly aided by innovations allowing dielectric scaling across both ends of the permittivity spectrum. This paper describes how new dielectric innovations beyond permi
Autor:
Ramanan V. Chebiam, Jasmeet S. Chawla, Seung Hoon Sung, Colin T. Carver, James S. Clarke, Mona Mayeh, Hui Jae Yoo, Bojarski Stephanie A, Robert B. Turkot, B. Krist, Manish Chandhok, Christopher J. Jezewski, M. J. Kobrinski, M. Harmes
Publikováno v:
2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC).
A process to achieve 6 nm minimum dimension interconnect wires is realized using standard 193 nm lithography. Various metals including copper are optimized to gap fill features, and tested for electrical performance and reliability. Measurements show
Publikováno v:
ECS Transactions. 2:13-18
Electrodeposition of copper in the presence of additives (e.g., a suppressor, an accelerator, and a leveler) is being used for the fabrication of on-chip copper interconnects. For current generation interconnects, the via and trench aspect ratios req
Autor:
Chin-Chang Cheng, Valery M. Dubin, Arnel M. Fajardo, Ramanan V. Chebiam, Rohan Akolkar, Florian Gstrein
Publikováno v:
Electrochimica Acta. 52:2891-2897
Various technical issues related to feature scaling and recent electrochemical technologies advances for on-chip copper interconnects at Intel are reviewed. Effects of additives on electroplating, as well as performance of novel Cu direct plating on
Autor:
James S. Clarke, Ramanan V. Chebiam, Seung Hoon Sung, Chris Jezewski, Bob Turkot, Hui Jae Yoo, Jasmeet S. Chawla, Colin T. Carver, Tronic Tristan A
Publikováno v:
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM).
Assessing metal gap fill capability and electrical behavior in patterned features ahead of full integration is valuable in interconnect process development as feature sizes scale beyond the 14 nm technology node. In this work a simple device is fabri
Autor:
John J. Plombon, Hui Jae Yoo, Narendra Lakamraju, Colin T. Carver, B. Krist, Rahim Kasim, Kanwal Jit Singh, Tejaswi K. Indukuri, Jasmeet S. Chawla, Kevin L. Lin, James S. Clarke, Mauro J. Kobrinsky, J. Bielefeld, Hazel Lang, Kabir Nafees, M. Harmes, Jessica M. Torres, E. Mays, Jacob Faber, Christopher J. Jezewski, Alan Myers, Ramanan V. Chebiam
Publikováno v:
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM).
Planar capacitors can quickly test material properties of metals and dielectrics for interconnects. A sidewall capacitor device is used to evaluate metal thin-film barriers. Etch stop planar capacitors in turn can test multi-layer etch stops, exposin
Autor:
Tejaswi K. Indukuri, John J. Plombon, Alan Myers, Mauro J. Kobrinsky, Narendra Lakamraju, Kevin L. Lin, Kanwal Jit Singh, Hui Jae Yoo, Jacob Faber, Christopher J. Jezewski, M. Harmes, B. Krist, James S. Clarke, Ramanan V. Chebiam, Hazel Lang, Colin T. Carver
Publikováno v:
IEEE International Interconnect Technology Conference.
A sidewall planar capacitor (SW CAP) vehicle is developed to closely simulate processing conditions for metal barrier and dielectric in an integrated structure. For a known tantalum barrier for copper on a low-K dielectric, SW CAP TDDB is similar to
Autor:
Christopher J. Jezewski, Kanwal Jit Singh, Florian Gstrein, Robert B. Turkot, Richard E. Schenker, Rohan Akolkar, Jasmeet S. Chawla, Ramanan V. Chebiam, Hui Jae Yoo, M. Harmes, Gary Allen, James S. Clarke, Colin T. Carver, B. Krist, Hazel Lang, Tejaswi K. Indukuri, Alan Myers
Publikováno v:
2013 IEEE International Interconnect Technology Conference - IITC.
A process to achieve 12 nm half-pitch interconnect structures in ultralow-k interlayer dielectric (ILD) is realized using standard 193 nm lithography. An optimized pattern transfer that minimizes unwanted distortion of ILD features is followed by cop
Autor:
Jennifer Lo, Steven Youkey, Jun Jiao, Valery M. Dubin, Ramanan V. Chebiam, Jocelyn Bush, Lifeng Dong
Publikováno v:
MRS Proceedings. 901
We recently developed a novel floating-potential dielectrophoretic method to selectively position individual single-walled carbon nanotubes between two floating electrodes while the bundles of nanotubes and impurities were attracted into the region b
Publikováno v:
Microscopy and Microanalysis. 10:394-395
Extended abstract of a paper presented at Microscopy and Microanalysis 2004 in Savannah, Georgia, USA, August 1–5, 2004.