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pro vyhledávání: '"Ralph H. J. M. Otten"'
Autor:
Ralph H. J. M. Otten
Publikováno v:
ISPD
The paper is a concise survey as well as an exposition of ideas about automation of layout design. Central is a discussion of imperatives of a layout design system suitable for VLSI. Of course, such a system has to take account of the embedding into
Autor:
Ralph H. J. M. Otten
Publikováno v:
Integration : the VLSI Journal, 32(1-2), 1-4. Elsevier
Publikováno v:
Integration : the VLSI Journal, 29(1), 1-24. Elsevier
A shift is proposed in the design of VLSI circuits. In conventional design, higher levels of synthesis produce a netlist, from which layout synthesis builds a mask specification for manufacturing. Timing analysis is built into a feedback loop to dete
Publikováno v:
Integration : the VLSI Journal, 29(1), 45-66. Elsevier
Recently, it has been shown that speed optimization for general acyclic network is efficiently solvable, and elegant ways of capturing several representations with base functions in a single network were introduced. This paper shows how to take advan
Publikováno v:
Power-Aware Architecting for data-dominated applications ISBN: 9781402064197
Power-Aware Architecting for data-dominated applications
Power-Aware Architecting for data-dominated applications
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1b8cf110e960c7b9ef0ea810c426c50b
https://doi.org/10.1007/978-1-4020-6420-3_2
https://doi.org/10.1007/978-1-4020-6420-3_2
Publikováno v:
Power-Aware Architecting for data-dominated applications ISBN: 9781402064197
Power-Aware Architecting for data-dominated applications
Power-Aware Architecting for data-dominated applications
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::209e664d48f5d9a80e7ef10ce615e733
https://doi.org/10.1007/978-1-4020-6420-3_4
https://doi.org/10.1007/978-1-4020-6420-3_4
Publikováno v:
Power-Aware Architecting for data-dominated applications ISBN: 9781402064197
Power-Aware Architecting for data-dominated applications
Power-Aware Architecting for data-dominated applications
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2928e4f684d6cf0cf44ac93236185df2
https://doi.org/10.1007/978-1-4020-6420-3_3
https://doi.org/10.1007/978-1-4020-6420-3_3
Publikováno v:
ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).
We present an analytic formula for repeater insertion in global interconnects that simultaneously minimizes silicon device area and power dissipation for a given performance /spl tau//sub crit//K where /spl tau//sub crit/ is the minimum possible dela
Publikováno v:
DATE
Advancing technology drives design technology and thus design automation (EDA). How to model interconnect, how to handle degradation of signal integrity and increasing power density are changing now, and have led to integrating logic and layout synth
Autor:
Ralph H. J. M. Otten
Publikováno v:
Proceedings of the 40th annual Design Automation Conference.