Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Rakesh Vallishayee"'
Autor:
Sharad Saxena, Christopher Hess, Michele Quarantelli, Alberto Piadena, Larg Weiland, Rakesh Vallishayee, Yuan Yu, Dennis Ciplickas, Tomasz Brozek, Andrzej Strojwas
Publikováno v:
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).
Evaluation of Truly Passive Crossbar Memory Arrays on Short Flow Characterization Vehicle Test Chips
Autor:
Christoph Dolainsky, Dennis Ciplickas, Tomasz Brozek, Rakesh Vallishayee, Christopher Hess, Khim Hong Ng, Hendrik Schneider, Meindert Lunenborg, Larg Weiland, Yuan Yu
Publikováno v:
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS).
More and more non volatile memory bit cell candidates are emerging which can be implemented between two metal layers in the BEOL process. Thus, short flow Characterization Vehicle® (CV®) Test Chips become beneficial for fast yield and endurance lea
Autor:
Rakesh Vallishayee, Nobuharu Yokoyama, Shia Yu, Tom Liu, Mike K. Pak, Stephen Lam, Tomasz Brozek
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 28:205-212
Electrical characterization remains a key element in technology development and manufacturing of integrated circuits. Contact chain is a well known part of the diagnostic set of test structures used across many generations of silicon processes. Imple
Autor:
Rakesh Vallishayee, Bob Yu, Meindert Lunenborg, Sharad Saxena, Cheng Jianjun, Christoph Dolainsky, Dennis Ciplickas
Publikováno v:
2013 IEEE International Electron Devices Meeting.
New technologies and integration schemes introduced over the last few generations have increased the sensitivity of transistor performance and variation to its layout and environment. This paper describes an infrastructure for efficient statistical c
Publikováno v:
2011 IEEE ICMTS International Conference on Microelectronic Test Structures.
Being successful in semiconductor manufacturing of sub 50nm devices requires controlling variability of device leakage. Full wafer monitoring is essential to provide significant data. The Device Leakage Scribe Characterization Vehicle (CV®) Test Chi
Publikováno v:
2009 IEEE International Conference on Microelectronic Test Structures.
A method of estimating the subthershold component of MOSFET off-state current (I offs ) using low-cost, low-resolution fast parallel parametric test is introduced. This method measures the subthreshold slope and uses it to estimate I offs . Measureme
Autor:
Stefan Jank, Vlad Temchenko, Paul G Karakatsanis, Ramana Veerasingam, Rakesh Vallishayee, Christoph Dolainsky, Xiaojing Yang, Bong-Ryoul Choi, Youval Nehmadi, Moshe Poyastro
Publikováno v:
2006 IEEE International Symposium on Semiconductor Manufacturing.
Deploying OPC that is robust over the process window is becoming more and more challenging as geometries shrinki ii. This challenge has a major impact in time-to-market and yield of new products. This paper describes a litho simulator calibration flo
Autor:
M. Renfro, Rakesh Vallishayee, Xiaolei Li, R.K. Nurani, Andrzej J. Strojwas, Dennis Ciplickas, R. Williams
Publikováno v:
IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168).
This paper presents a novel approach to the modeling of defect related yield losses in reconfigurable memory circuits. The proposed approach is based on the critical area extracted from the memory layout and the in-line defect inspection data. A comp
Autor:
Roland Ruehl, Rakesh Vallishayee, Wojtek Wojciak, Dennis Ciplickas, Mariusz Niewczas, Brian E. Stine
Publikováno v:
SPIE Proceedings.
This paper presents the result of an extension to the concept of Micro-Yield modeling. We have developed a design attribute extraction and yield prediction software system that - given the characterization of a semiconductor process via complex test
Autor:
Rakesh Vallishayee, Vikas Mehrotra, Duane S. Boning, Shiou Lin Sam, Sani R. Nassif, Anantha P. Chandrakasan
Publikováno v:
DAC
We present a methodology to study the impact of spatial pattern dependent variation on circuit performance and implement the technique in a CAD framework. We investigate the effects of interconnect CMP and poly CD device variation on interconnect del