Zobrazeno 1 - 10
of 64
pro vyhledávání: '"Rajendran Panda"'
Publikováno v:
EDA for IC Implementation, Circuit Design, and Process Technology ISBN: 9781315221694
Industrial Information Technology ISBN: 9780849379246
Industrial Information Technology ISBN: 9780849379246
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::dfda52877d4359b11e3c13d597f6483f
https://doi.org/10.1201/9781420007954-20
https://doi.org/10.1201/9781420007954-20
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25:1038-1046
This paper presents a linear system formulation for evaluating full-chip electromigration (EM) risk in general (straight line, tree, and mesh) wiring topologies, considering stress-induced backflow of metal ions. The system of equations is based on s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::08a674f0c5b33854e611b5039405efaa
https://doi.org/10.1109/tcad.2005.855941
https://doi.org/10.1109/tcad.2005.855941
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25:144-154
Power-distribution networks of very large-scale integrated (VLSI) chips should be designed carefully to ensure reliable performance. A sound power network requires an adequate number of power-supply input connections (pads and pins). Placing them at
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::22adced4508c26f8bba6a69cc7b79575
https://doi.org/10.1109/tcad.2005.852459
https://doi.org/10.1109/tcad.2005.852459
Autor:
Ilan Algor, Vladimir Zolotov, David Blaauw, M. Becer, Rajendran Panda, Ibrahim N. Hajj, Chanhee Oh
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 23:1670-1677
Gate sizing is a practical and a feasible crosstalk noise correction technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that, by increasing a driver size, no
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::52689cd7e55e2374f28a4e087d6eb659
https://doi.org/10.1109/tcad.2004.836736
https://doi.org/10.1109/tcad.2004.836736
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 23:488-497
Signal integrity closure is one of the key challenges in deep submicron physical design. In this paper, we propose a physical design methodology which includes signal integrity management through crosstalk noise analysis and repair at multiple phases
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::486a6c42a5712c491532650ae806177a
https://doi.org/10.1109/tcad.2004.825855
https://doi.org/10.1109/tcad.2004.825855
Publikováno v:
IEEE Design & Test of Computers. 20:16-22
Although it is tempting to think of the power grid as an independent medium of the transfer of energy from the package to the devices in the IC, some second-order technology-related effects can sometimes cause unforeseen problems. This article focuse
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b10b70492a6baca7c603732d22f58a7f
https://doi.org/10.1109/mdt.2003.1198681
https://doi.org/10.1109/mdt.2003.1198681
Publikováno v:
SLIP
One of the critical challenges in today's high performance IC design is to take noise into account as early as possible in the design cycle. Current noise analysis tools [1, 7} are effective at analyzing and identifying noise in the post-route design
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4bf3da66b451ec5d36055ff82814673a
https://doi.org/10.1109/tcad.2002.807892
https://doi.org/10.1109/tcad.2002.807892
Autor:
Kaushik Gala, Vladimir Zolotov, David Blaauw, Sachin S. Sapatnekar, Min Zhao, Rajendran Panda, Haitian Hu
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 22:49-66
In this paper, a precorrected-fast-Fourier-transform (FFT) approach for fast and highly accurate simulation of circuits with on-chip inductance is proposed. This work is motivated by the fact that circuit analysis and optimization methods based on th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7b00759dee2acbdeab3323736cd93c77
https://doi.org/10.1109/tcad.2002.805719
https://doi.org/10.1109/tcad.2002.805719
Publikováno v:
Analog Integrated Circuits and Signal Processing. 35:133-142
Signal integrity has become a critical issue in the design of high-performance circuits. Noise on a net arises both through propagation of noise from previous stages through the driver gate of the net and through injection of new noise through coupli
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5d5c3334aa78088a68922a2bacfeffd5
https://doi.org/10.1023/a:1024174415034
https://doi.org/10.1023/a:1024174415034
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 10:79-90
Presents a new approach for the estimation and optimization of standby power dissipation in large MOS digital circuits. We introduce a new approach for accurate and efficient calculation of the average standby or leakage current in large digital circ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eae8afeb0d19d4e190368cd6129c3f17
https://doi.org/10.1109/92.994980
https://doi.org/10.1109/92.994980