Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Raja Athimulam"'
Autor:
P. Schuddinck, Stefan Kubicek, Nadine Collaert, M. Garcia-Bardon, Aaron Thean, Raja Athimulam, Steven Demuynck, Ingrid Debusschere, Mustafa Badaroglu, L. Altimime, Naoto Horiguchi, Diederik Verkest, Michele Stucchi, Thomas Chiarella, Abdelkarim Mercha, Arindam Mallik, Andriy Hikavyy
Publikováno v:
2012 International Electron Devices Meeting.
It is shown that the performance impact of middle-of-line (MOL) patterning process variations can be reduced by 30% by relaxing the standard cell gate pitch by 10% in both 20nm bulk planar (BPL) and 14nm bulk finFET (BFF). Tungsten can safely replace
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9142fc91c8dced46e5a8bd7512c14fa3
https://doi.org/10.1109/iedm.2012.6479101
https://doi.org/10.1109/iedm.2012.6479101
Autor:
Inge Vaesen, Thomas Witters, Kristof Kellens, Anabela Veloso, Raja Athimulam, Aaron Thean, E. Vecchio, Farid Sebaai, Lars-Ake Ragnarsson, Hugo Bender, X. Shi, Katia Devriendt, A. Dangol, Vasile Paraschiv, Tom Schram, Thomas Chiarella, Stephan Brus, Harold Dekkers, Thierry Conard, Eddy Simoen, Moon Ju Cho, Annemie Van Ammel, Guillaume Boccardi, Soon Aik Chew, Olivier Richard, Nancy Heylen, Naoto Horiguchi, Jae Woo Lee, Higuchi Yuichi, Hiroaki Arimura, Philippe Roussel
Publikováno v:
Japanese Journal of Applied Physics. 53:04EA04
We report on aggressively scaled replacement metal gate, high-k last (RMG-HKL) planar and multi-gate fin field-effect transistor (FinFET) devices, systematically investigating the impact of post high-k deposition thermal (PDA) and plasma (SF6) treatm
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5334a012afd35dfbc08d61bef3db803e
https://doi.org/10.7567/jjap.53.04ea04
https://doi.org/10.7567/jjap.53.04ea04
Autor:
V. Paraschiv, Hubert Hody, Emma Vecchio, Gustaf Winroth, S. Locorotondo, Werner Boullart, Raja Athimulam
Publikováno v:
Journal of Micro/Nanolithography, MEMS, and MOEMS. 12:041306
In this paper, we report a double patterning process resulting in amorphous silicon (a-Si) gate lines with a thickness of 80nm and a lateral critical dimension (CD) below 30nm. We present a full stack for a double patterning approach for etch transfe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b35a1023a51019a4f7b484cbd85c301e
https://doi.org/10.1117/1.jmm.12.4.041306
https://doi.org/10.1117/1.jmm.12.4.041306