Zobrazeno 1 - 10
of 146
pro vyhledávání: '"Rainer Dömer"'
Autor:
Emad Malekzadeh Arasteh, Rainer Dömer
Publikováno v:
Analysis, Estimations, and Applications of Embedded Systems ISBN: 9783031264993
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::344b5f3f548f6920c969dd90aab76756
https://doi.org/10.1007/978-3-031-26500-6_10
https://doi.org/10.1007/978-3-031-26500-6_10
Publikováno v:
International Journal of Parallel Programming. 49:200-215
To preserve the SystemC semantics under parallel discrete event simulation, a compiler based approach statically analyzes race conditions in the design model. However, there are severe restrictions: the source code for the input design must be availa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e447bc8ff92ecfc54f2de21904788564
https://doi.org/10.1007/s10766-020-00668-w
https://doi.org/10.1007/s10766-020-00668-w
Autor:
Emad Malekzadeh Arasteh, Rainer Dömer
Publikováno v:
FDL
For effective embedded system design, transaction level modeling (TLM) must explicitly expose any available parallelism in the application. Traditional TLM in SystemC utilizes channels for communication and synchronization between concurrent modules,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::579db0f3cff44b056be07cc70c34219c
https://doi.org/10.1109/fdl53530.2021.9568385
https://doi.org/10.1109/fdl53530.2021.9568385
Autor:
Rainer Dömer, Zhongqi Cheng
Publikováno v:
ACM Transactions on Embedded Computing Systems. 18:1-20
The SystemC TLM-2.0 standard is widely used in modern electronic system level design for better interoperability and higher simulation speed. However, TLM-2.0 has been identified as an obstacle for parallel SystemC simulation due to the disappearance
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::63a7f3afab97a9cf209cd4d6d80c2985
https://doi.org/10.1145/3358194
https://doi.org/10.1145/3358194
Publikováno v:
A Journey of Embedded and Cyber-Physical Systems ISBN: 9783030474867
A Journey of Embedded and Cyber-Physical Systems
A Journey of Embedded and Cyber-Physical Systems
The IEEE SystemC language is widely used in industry and academia to model and simulate system-level designs. Despite the availability of multi- and many-core host processors, however, the Accellera reference simulator is still based on sequential di
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8e956948a305960934f339ff6dc71dc4
https://doi.org/10.1007/978-3-030-47487-4_7
https://doi.org/10.1007/978-3-030-47487-4_7
Publikováno v:
ASP-DAC
Out-of-order Parallel Discrete Event Simulation (OoO PDES) is an advanced simulation approach that efficiently verifies and validates SystemC models. To preserve the simulation semantics, OoO PDES performs a conservative event delivery strategy which
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::63723554d90a0359a27c2e50349caee4
https://doi.org/10.1109/asp-dac47756.2020.9045492
https://doi.org/10.1109/asp-dac47756.2020.9045492
Publikováno v:
Lecture Notes in Electrical Engineering ISBN: 9783030315849
FDL
FDL
IEEE SystemC is one of the most popular standards for system level design. With the Recoding Infrastructure for SystemC (RISC), a SystemC model can be executed at segment level in parallel. Although the parallel simulation is generally faster than it
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::59c50c3e922433d47b84a35eeedb7ace
https://doi.org/10.1109/fdl.2018.8524058
https://doi.org/10.1109/fdl.2018.8524058
Publikováno v:
DATE
Many parallel SystemC approaches expect a thread safe and conflict free model from the designer. Alternatively, an advanced compiler can identify and avoid possible parallel access conflicts. While manual conflict resolution can theoretically be more
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::11fd062b02d8085a98f1f0eaa8072a7f
https://doi.org/10.23919/date.2018.8342034
https://doi.org/10.23919/date.2018.8342034
Autor:
Chen, Weiwei
Publikováno v:
Out-of-Order Parallel Discrete Event Simulation for Electronic System-Level Design; 2015, p137-145, 9p
Publikováno v:
DAC
Most parallel SystemC approaches have two limitations: (a) the user must manually separate all parallel threads to avoid data corruption due to race conditions, and (b) available hardware vector units are not utilized. In this paper, we present an ad
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::09a3e504848924d1cde48e20cb32ccd5
https://doi.org/10.1145/3061639.3062243
https://doi.org/10.1145/3061639.3062243