Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Rahim Kasim"'
Autor:
Rahim Kasim, Mauro J. Kobrinsky
Publikováno v:
IRPS
In this paper, we describe both evolutionary and disruptive Back End Of Line innovations needed to enable scaling and performance improvements, and their reliability impact.
Autor:
Rahim Kasim, Madhavan Atul, D. Kencke, J. R. Weber, G. W. Zhang, C. Perini, J. Palmer, C.-Y. Lin
Publikováno v:
2020 IEEE International Interconnect Technology Conference (IITC).
This paper focuses on the study of Co/Low-k dielectric TDDB (Time Dependent Dielectric Breakdown) in Intel’s 10nm process technology. We demonstrate that 36nm/40nm pitch Cobalt interconnects with Low-k dielectric successfully meet our technology TD
Autor:
D. Towner, C. Ryder, M. A. Blount, C. Auth, K. Sethi, J. R. Weber, Che-Yun Lin, U. E. Avci, A. J. Welsh, C. M. Pelto, A. Kundu, R. Grover, Rahim Kasim, D. Seghete, A. Schmitz, J. Hicks
Publikováno v:
IRPS
We present a high density MIM decoupling capacitor that enables improved microprocessor performance by providing robust on-chip power supply droop reduction. The MIM dielectric is fabricated using ALD-deposited HfO 2 -Al 2 O 3 and HfO 2 -ZrO 2 high-k
Autor:
Benjamin J. Orr, Nathan Jack, C. Auth, A. Schmitz, Tony Acosta, Steven S. Poon, Che-Yun Lin, Abdur Rahman, C. AnDyke, Rahim Kasim, K. Downes, G. McPherson, Sunny Chugh, Madhavan Atul, D. Nminibapiel, Adam Neale, K. Sethi, Seung Hwan Lee, S. Ramey, Tanmoy Pramanik, Michael L. Hattendorf, Emre Armagan, J. Palmer, Subhash M. Joshi, Ian R. Post, C. M. Pelto, P. Nayak, Yeoh Andrew W, G. Martin, Gerald S. Leatherman, H. Wu, N. Seifert, A. Lowrie, R. Grover, H. Mao
Publikováno v:
IRPS
We provide a comprehensive overview of the reliability characteristics of Intel’s 10+ logic technology. This is a 10 nm technology featuring the third generation of Intel’s FinFETs, seventh generation of strained silicon, fifth generation of high
Autor:
Rahim Kasim, J. Palmer, A. Schmitz, I. Tsameret, F. Pan, C. Auth, Flavio Griggio, Yeoh Andrew W, Gerald S. Leatherman, Joseph M. Steigerwald, J. Hicks, J. Shin, A. Madhavan, N. Toledo
Publikováno v:
IRPS
This paper discusses the reliability of a new metallization scheme for 10nm back end of line (BEOL) local interconnect. Electromigration (EM) and time dependent dielectric breakdown (TDDB) on cobalt fill interconnects are investigated. Significant in
Publikováno v:
Advanced Materials Research. :1503-1507
In this work, we present the development of MEMS switch array and ZnO nanowire-based sensor technology to detect multiple analytes in a sensitive manner. A novel approach that incorporates the advantages of MEMS technology with highly sensitive ZnO n
Publikováno v:
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2011:000926-000951
This paper provides development of MEMS switches and packaging of MEMS to test radio frequency circuits used in wireless products such as cell phones and network routers. We discuss fabrication of MEMS using low voltage magnetic materials and their c
Autor:
Rahim Kasim, Bruce Kim
Publikováno v:
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2010:001808-001840
This article presents the design, fabrication, and packaging of advanced MEMS in high power applications. The advanced MEMS devices are used as a power sensor to detect high current in a distributed power network. We designed and fabricated an M × N
Autor:
Patel Reken, P. Plekhanov, S. Rajamani, P. Reese, Conor P. Puls, Muhammet Uncuer, Rahim Kasim, E. Hwang, M. Agostinelli, M. Bost, Swaminathan Sivakumar, S. Nigam, Sanjay Natarajan, P. Charvat, S. Kosaraju, M. Prince, D. Rao, B. Song, M. Yang, S. Williams, P. Yashar, K. S. Lee, Pulkit Jain, I. Jin, Q. Fu, H. Hiramatsu, Kevin J. Fischer, Max M. Heckscher, R. McFadden, V. Chikarmane, Haran Mohit K, A. Rosenbaum, Huichu Liu, D. Bahr, C. Ganpule, C. Pelto, C. Allen
Publikováno v:
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM).
We describe here Intel's 14nm high-performance logic technology interconnects and back end stack featuring 13 metal layers and a tri-metal laminated metal-insulator-metal (MIM) capacitor. For the first time on a logic product in high volume, multiple
Autor:
John J. Plombon, Hui Jae Yoo, Narendra Lakamraju, Colin T. Carver, B. Krist, Rahim Kasim, Kanwal Jit Singh, Tejaswi K. Indukuri, Jasmeet S. Chawla, Kevin L. Lin, James S. Clarke, Mauro J. Kobrinsky, J. Bielefeld, Hazel Lang, Kabir Nafees, M. Harmes, Jessica M. Torres, E. Mays, Jacob Faber, Christopher J. Jezewski, Alan Myers, Ramanan V. Chebiam
Publikováno v:
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM).
Planar capacitors can quickly test material properties of metals and dielectrics for interconnects. A sidewall capacitor device is used to evaluate metal thin-film barriers. Etch stop planar capacitors in turn can test multi-layer etch stops, exposin