Zobrazeno 1 - 10
of 23
pro vyhledávání: '"Rafik Guindi"'
Autor:
Islam Abdo, Christos Trompoukis, Ivan Gordon, Ounsi El Daif, Loic Tous, Valerie Depauw, Rafik Guindi
Publikováno v:
IEEE Journal of Photovoltaics. 5:1319-1324
In the frame of the development of thin crystalline silicon solar cell technologies, surface nanopatterning of silicon is gaining importance. Its impact on the material quality is, however, not yet fully controlled.We investigate here the influence o
Autor:
Hossam ElAnzeery, Marc Meuris, David Cheyns, Souhaib Oueslati, Rafik Guindi, Jef Poortmans, Khaled Ben Messaoud, Guy Brammertz, Marie Buffiere, Ounsi El Daif
Publikováno v:
physica status solidi (RRL) - Rapid Research Letters. 9:338-343
Cu2ZnSi(S,Se)4 and Cu2Si(S,Se)3 are potential materials to obtain cost effective high band gap absorbers for tandem thin film solar cell devices. A method to synthesize Cu2SiS3, Cu2SiSe3and Cu2ZnSiSe4thin film absorbers is proposed. This method is ba
Autor:
Jef Poortmans, Marie Buffiere, Bas J. Kniknie, Marc Meuris, Souhaib Oueslati, Ounsi El Daif, Khaled Ben Messaoud, Rafik Guindi, Dries Agten, Hossam ElAnzeery, Guy Brammertz
Publikováno v:
physica status solidi (a). 212:1984-1990
Cu2nSnSe4 (CZTSe) thin film solar cells are promising emergent photovoltaic technologies based on low-bandgap absorber layer with high absorption coefficient. To reduce optical losses in such devices and thus improve their efficiency, numerical simul
Publikováno v:
HLDVT
System Verilog Assertions (SVA) is widely used by hardware designers and verification engineers to apply Assertion Based Verification (ABV) methodology on their hardware designs. However, the complexity in understanding different protocol standards i
Publikováno v:
IDT
Verification architects need to make use of randomness supported by System Verilog and be able to define a generic path for the test to follow. This path represents a subset of features, and allows the test to randomly explore the design space to exp
Publikováno v:
ICECS
Design rules verification is an essential stage in the Process Design Kit (PDK) release for any fab. Since achieving high yield is the target of any fab, the design rules should ensure this. Design rules violations happening after fabrication lead to
Autor:
Muhammad M. Khellah, Rafik Guindi, Ahmed M. Ammar, Ethan Shih, Carlos Tokunaga, James W. Tschanz
Publikováno v:
SoCC
Power supply noise has become a major challenge for proper operation of circuits with continuous scaling of CMOS technology along with supply voltage scaling. Conventional passive decoupling capacitors exhibit significant die area penalty resulting i
Autor:
Dries Van Gestel, Christos Trompoukis, Rafik Guindi, Islam Abdo, Valerie Depauw, Ivan Gordon, Ounsi El Daif, Jan Deckers, Loic Tous
The integration of two-dimensional (2D) periodic nanopattern defined by nanoimprint lithography and dry etching into aluminum induced crystallization (AIC) based polycrystalline silicon (Poly-Si) thin film solar cells is investigated experimentally.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0af20c14b27ade6c94ee8ac358c9d279
http://arxiv.org/abs/1507.08341
http://arxiv.org/abs/1507.08341
Publikováno v:
MTV
System Verilog Assertions (SVA) is widely used by hardware designers and verification engineers to apply Assertion Based Verification (ABV) methodology on their hardware designs. However, the ambiguity of design specifications specified by different