Výsledky vyhledávání

Dissertation/ Thesis

Desenvolvimento de um sistema dinamicamente reconfigurável baseado em redes intra-chip e ferramenta para posicionamento de módulos.

Autor: Raffo Jara, Mario Andrés

Os sistemas dinamicamente reconfiguráveis (SDRs) são uma alternativa para o desenvolvimento de sistemas sobre silício baseados em circuitos programáveis (SoPC), cujo principal beneficio é o bom aproveitamento da área do dispositivo. Sendo neles

Externí odkaz: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-11082010-100838/

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A Flexible UVM-Based Verification Framework Reusable with Avalon, AHB, AXI and Wishbone Bus Interfaces for an AES Encryption Module

Autor: Mario Raffo-Jara, Edward Mitacc-Meza, Carlos Silva-Cardenas, Frank Plasencia-Balabarca

Publikováno v: LATS

The fast and continuous development of digital circuits lead to complex and unpredictable designs which have to be submitted under high-standard verification processes. Furthermore, not only the core modules have evolved over the time, but also the c

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::246734e1fb649e9ecb7d42946cf00d4f
https://doi.org/10.1109/latw.2019.8704549

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Robust Functional Verification Framework Based in UVM Applied to an AES Encryption Module

Autor: Edward Mitacc-Meza, Frank Plasencia-Balabarca, Carlos Silva-Cardenas, Mario Raffo-Jara

Publikováno v: NGCAS

This Since the past century, the digital design industry has performed an outstanding role in the development of electronics. Hence, a great variety of designs are developed daily, these designs must be submitted to high standards of verification in

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e2b6db2cdd35263cd81efe52ae5fd1a2
https://doi.org/10.1109/ngcas.2018.8572292

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Alternative functional verification methodology for low and medium level designs (Applied to an AES encryption module)

Autor: Mario Raffo-Jara, Edward Mitacc-Meza, Frank Plasencia-Balabarca, Carlos Silva-Cardenas

Publikováno v: LATS

Over the time, the development of the digital design field has increased dramatically and nowadays many different circuits and systems are designed for multiple purposes in short time lapses. However, this development has not been based only in the e

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::29e43a3cb1590da9faf6229a9ec93068
https://doi.org/10.1109/latw.2018.8349672

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An efficient hardware architecture of the H.264/AVC Half and Quarter-Pixel Motion Estimation for real-time High-Definition Video streams

Autor: Ernesto Villegas Castillo, Mario Raffo Jara, Carlos Silva Cardenas

Publikováno v: 2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS).

The H.264/AVC is the newest digital video compression standard developed by the Joint Video Team (JVT). This standard includes new algorithms as the Fractional Motion Estimation that enhances the coding efficiency and compression rate of video sequen

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a92a740258de6c942c1b3a9dea42169d
https://doi.org/10.1109/lascas.2012.6180302

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Dissertation/ Thesis

Desenvolvimento de um sistema dinamicamente reconfigurável baseado em redes intra-chip e ferramenta para posicionamento de módulos.

Autor: Mario Andrés Raffo Jara

Publikováno v: Biblioteca Digital de Teses e Dissertações da USPUniversidade de São PauloUSP.

Externí odkaz: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-11082010-100838/

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Development of a dynamically reconfigurable systems under noc and CAD for modules mapping

Autor: Mario Andrés, Raffo Jara

Publikováno v: Biblioteca Digital de Teses e Dissertações da USP
Universidade de São Paulo (USP)
instacron:USP

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e41ad97df9444ea2745cfbd174b4fb2f

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Conference

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Conference

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Conference

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