Zobrazeno 1 - 10
of 1 000
pro vyhledávání: '"RADIATION hardening (Electronics)"'
Publikováno v:
Electronics Letters, Vol 60, Iss 23, Pp n/a-n/a (2024)
Abstract In this paper, a radiation hardened by design StrongARM comparator is proposed to mitigate the radiation effects. With 12 additional transistors compared to the conventional one, the proposed structure shows much higher immunity to single‐
Externí odkaz:
https://doaj.org/article/faee7d84b90640c39899e1ae1fd7e1ae
Publikováno v:
Materials at High Temperatures. Sep2018, Vol. 35 Issue 5, p469-481. 13p. 2 Color Photographs, 19 Diagrams, 5 Charts.
Autor:
Yan, Aibin1 abyan@mail.ustc.edu.cn, Wu, Zhen1 2262076636@qq.com, Guo, Jing2 guojing861229@163.com, Song, Jie1 909944599@qq.com, Wen, Xiaoqing3 wen@cse.kyutech.ac.jp
Publikováno v:
IEEE Transactions on Reliability. Mar2019, Vol. 68 Issue 1, p354-363. 10p.
Autor:
Peng, Chao1, Hu, Zhiyuan2, En, Yunfei1, Chen, Yiqiang1, Lei, Zhifeng1, Zhang, Zhangang1, Zhang, Zhengxuan2, Li, Bin3
Publikováno v:
IEEE Transactions on Nuclear Science. Mar2018, Vol. 65 Issue 3, p877-883. 7p.
Autor:
Ochedowski, O.1, Marinov, K.1, Wilbs, G.2, Keller, G.2, Scheuschner, N.3, Severin, D.4, Bender, M.4, Maultzsch, J.3, Tegude, F. J.2, Schleberger, M.1
Publikováno v:
Journal of Applied Physics. Jun2013, Vol. 113 Issue 21, p214306. 7p. 3 Color Photographs, 3 Graphs.
Akademický článek
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Autor:
Lazzari, Cristiano1 lazzari@inesc-id.pt, Wirth, Gilson2 wirth@inf.ufrgs.br, Kastensmidt, Fernanda2 fglima@inf.ufrgs.br, Anghel, Lorena3 lorena.anghel@imag.fr, Reis, Ricardo2 reis@inf.ufrgs.br
Publikováno v:
Electrical Engineering. Mar2012, Vol. 94 Issue 1, p11-18. 8p. 3 Diagrams, 3 Charts, 1 Graph.
Autor:
McHale, John
Publikováno v:
Military & Aerospace Electronics. Jun2010, Vol. 21 Issue 6, p24-33. 6p.
Publikováno v:
IET Circuits, Devices and Systems, Vol 16, Iss 2, Pp 178-188 (2022)
Abstract Single‐event transients (SETs) due to heavy‐ion (HI) strikes adversely affect the electronic circuits in the sub‐100 nm regime in the radiation environment. This study proposes techniques to mitigate SETs in CMOS voltage‐controlled o
Externí odkaz:
https://doaj.org/article/bfe13102725d49c19c5fd63e69f3fb1b
Autor:
Goiffon, Vincent1, Rolando, Sebastien1, Corbiere, Franck1, Rizzolo, Serena1, Chabane, Aziouz1, Girard, Sylvain2, Baer, Jeremy1, Estribeau, Magali1, Magnan, Pierre1, Paillet, Philippe3, Van Uffelen, Marco4, Mont Casellas, Laura4, Scott, Robin5, Gaillardin, Marc3, Marcandella, Claude3, Marcelot, Olivier1, Allanche, Timothe2
Publikováno v:
IEEE Transactions on Nuclear Science. Jan2017, Vol. 64 Issue 1, part 1, p45-53. 9p.