Zobrazeno 1 - 6
of 6
pro vyhledávání: '"R.W. Badeau"'
Autor:
W.V. Herrick, J.F. Brown, D.R. Deverell, Elizabeth M. Cooper, T.C. Fischer, G.M. Uhler, Hamid Partovi, R.I. Bahar, M.A. Case, M.A. Delaney, V. Peng, A. Jain, J.E. Meyer, J.J. Ellis, R.P. Preston, M.K. Gowan, D. Bernstein, T.F. Fox, D.G. Miner, C. Somanathan, R.L. Stamm, R.W. Badeau, W.R. Wheeler, N.D. Wade, J.H. Edmonson, S.C. Thierauf, R.W. Castelino, L.L. Biro, W.J. Bowhill, P.E. Gronowski
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:1585-1598
A macropipelined CISC microprocessor was implemented in a 0.75- mu m CMOS 3.3-V technology. The 1.3-million-transistor custom chip measures 1.62*1.46 cm/sup 2/ and dissipates 16.3 W. The 100-MHz parts were benchmarked at 50 SPEC marks. The on-chip cl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1035e33d8131e9f2bca7f858e00dcf5b
https://doi.org/10.1109/4.165340
https://doi.org/10.1109/4.165340
Autor:
M.J. Smith, S. Felix, Shane L. Bell, J.D. Pickholtz, R.W. Badeau, Swati Mehta, M.K. Gowan, D.B. Jackson, Matthew H. Reilly, R. Gammack, Paul E. Gronowski, S.V. Morton, William J. Bowhill, L.L. Biro, D.W. Bailey, V. Germini, R.P. Preston, D.E. Dever
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
A 250M transistor microprocessor implements the Alpha instruction set and features 8-wide superscalar issue and simultaneous multithreading in a 0.125/spl mu/m SOI process. Performance is estimated at over three times that of the previous design.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5e2a802a8f4a58c87d094dcd0d3f4bc4
https://doi.org/10.1109/isscc.2002.992247
https://doi.org/10.1109/isscc.2002.992247
Autor:
T.C. Fischer, William J. Bowhill, R.I. Bahar, J. Edmondson, W.R. Wheeler, A. Jain, D.R. Deverell, M.K. Gowan, R. Castelino, M. Uhler, J.F. Brown, R.P. Preston, Paul E. Gronowski, Elizabeth M. Cooper, V. Peng, W.V. Herrick, M.A. Case, C. Somanathan, S.C. Thierauf, N.D. Wade, J.J. Ellis, M.A. Delaney, T. Fox, D. Bernstein, Hamid Partovi, J.E. Meyer, R.L. Stamm, R.W. Badeau, L.L. Biro, D. Miner
Publikováno v:
1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
A macropipelined CISC microprocessor implemented in a 0.75- mu m CMOS 3.3-V three-metal-layer technology is described. The 1.3 M-transistor custom chip measures 1.62*1.46 cm/sup 2/, dissipates 18 W (peak), and is packaged in a 339-pin PGA. The chip i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b081410b71c53e0916a70529d7ddb059
https://doi.org/10.1109/isscc.1992.200433
https://doi.org/10.1109/isscc.1992.200433
Akademický článek
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Akademický článek
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Autor:
Krzysztof Iniewski
CMOS Processors and Memories addresses the-state-of-the-art in integrated circuit design in the context of emerging computing systems. New design opportunities in memories and processor are discussed. Emerging materials that can take system performan
