Zobrazeno 1 - 10
of 358
pro vyhledávání: '"R.J. Bolton"'
Publikováno v:
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 48:789-793
A low latency architecture to compute the multiplicative inverse and division in a finite field GF (2/sup m/) is presented. Compared to other proposals with the same complexity, this circuit has lower latency and can be used in error-correction or cr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bd3ea2b3543195648d60f1b91ce1ac9f
https://doi.org/10.1109/82.959871
https://doi.org/10.1109/82.959871
Publikováno v:
CCECE
This paper presents a reconfigurable Body Area Network (BAN) system that can be used to monitor human vital signs and identify abnormalities. The identification of clinically significant patterns in electrocardiogram (ECG) data is the application use
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8ab6302393c137433804f00e258de54d
https://doi.org/10.1109/ccece.2013.6567769
https://doi.org/10.1109/ccece.2013.6567769
Publikováno v:
International Journal of Electronics. 74:251-263
A new structure is proposed for the realization of multiple-valued logic (MVL) functions. Multiple-valued logic levels are represented in terms of current values, which represent the inputs and the outputs of the MVL circuits. Binary voltage signals
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::367b7647d5461931354b7084137a53bf
https://doi.org/10.1080/00207219308925832
https://doi.org/10.1080/00207219308925832
Publikováno v:
IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications. 40:503-514
A CMOS circuit implementation of a functionally complete multiple-valued logic (MVL) set of operators is proposed. The set consists of literal, cycle, complement of literal, complement of cycle, min, and tsum operators. In all of the circuits, multip
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::544bc69196fd0b7ce5aca60434218d39
https://doi.org/10.1109/81.242320
https://doi.org/10.1109/81.242320
Publikováno v:
IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications. 40:515-522
For pt. I see ibid vol. 40, no. 8 p 503-14 (1993). The performance of the set of operators proposed in pt. I is compared with existing sets of operators for the realization of multiple-valued logic (MVL) functions. In pt. I, a set of operators was pr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::16016042ca26934cade6987a643d6f00
https://doi.org/10.1109/81.242321
https://doi.org/10.1109/81.242321
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:184-190
A node-parallel Viterbi decoding architecture and bit-serial processing and communication are presented. An important aspect of this structure is that short-constraint-length decoders may be interconnected, without loss of throughput, to implement a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ddad00874bd09468e910d35a838c5f64
https://doi.org/10.1109/4.127341
https://doi.org/10.1109/4.127341
Publikováno v:
2007 Canadian Conference on Electrical and Computer Engineering.
This paper describes an approach to low-level VHDL modeling of digital-to-analog converter (DAC). A 12-bit DAC was modeled and simulated with Cadence NC-Sim simulator to test the feasibility of the approach. The simulation result shows that the appro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ddf3d9f31e5e1c49c21bf778c9505d5e
https://doi.org/10.1109/ccece.2007.28
https://doi.org/10.1109/ccece.2007.28
Autor:
Daniel Teng, R.J. Bolton
Publikováno v:
Canadian Conference on Electrical and Computer Engineering, 2005..
Since there are no standard benchmark functions available for comparing multiple-valued logic (MVL) designs, benchmark functions for binary logic design are often used for performance analysis of MVL circuits. An alternative would be to test all the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d45a3e469004362ced214213c9e9a149
https://doi.org/10.1109/ccece.2005.1556932
https://doi.org/10.1109/ccece.2005.1556932
Autor:
D. Laturnas, R.J. Bolton
Publikováno v:
Canadian Conference on Electrical and Computer Engineering, 2005..
Firewalls filter information as it flows through a network. This filter can be implemented in hardware or software and can be used to protect computers from unwanted access. While software firewalls are considered easier to set up and use, hardware f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2012e5e925e284874e87722e2ffb1a05
https://doi.org/10.1109/ccece.2005.1556933
https://doi.org/10.1109/ccece.2005.1556933
Autor:
R.J. Bolton, D.H.Y. Teng
Publikováno v:
ISMVL
This paper presents a statistical approach for fast comparison of multiple-valued logic (MVL) designs. Since there are no standard benchmark functions available for MVL, the benchmark functions for binary logic were used for performance analysis of M
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::119e418b49430881867480fc56a4dc88
https://doi.org/10.1109/ismvl.2005.17
https://doi.org/10.1109/ismvl.2005.17