Zobrazeno 1 - 10
of 65
pro vyhledávání: '"R.H. Klenke"'
Publikováno v:
Proceedings of the 34th Design Automation Conference.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::533e8902063bbd34b5b1f723e01c12af
https://doi.org/10.1109/dac.1997.597141
https://doi.org/10.1109/dac.1997.597141
Publikováno v:
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit.
The design and implementation of an object-oriented topologically partitioned parallel automatic test pattern generation (ATPG) system, ES-TPS, on a multiple-instruction multiple-data (MIMD) distributed-memory multiprocessor are described. The ATPG s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1af93eeb5c0c1bc58e8f84257cb54ec2
https://doi.org/10.1109/asic.1992.270264
https://doi.org/10.1109/asic.1992.270264
Publikováno v:
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit.
The Stream Memory Controller (SMC) is an experimental memory interface which allows hardware-assisted memory access reordering for vector computations in order to maximize the efficiency of the system memory bus. This paper describes the design and t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f1794e1c4d13ef08d91d9dcee3093aa9
https://doi.org/10.1109/asic.1994.404519
https://doi.org/10.1109/asic.1994.404519
Publikováno v:
Proceedings VHDL International Users' Forum. Fall Conference.
Using VHDL, it is possible to model systems at many different levels of detail. The various modeling levels (performance, behavioral, etc.) can also be intermixed to create mixed-level models. The paper describes the watch-and-react interface which w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1b0a749ad3b3fc1faa87ce95cc1ceab9
https://doi.org/10.1109/viuf.1997.623926
https://doi.org/10.1109/viuf.1997.623926
Publikováno v:
Proceedings of Eighth International Application Specific Integrated Circuits Conference.
This paper describes the design process used in developing a Stream Memory Controller (SMC). The SMC can reorder processor-memory accesses dynamically to increase the effective memory bandwidth for vector operations. A 132-pin ASIC was implemented in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1f278d169206bfd03581dd4f7c9ee4af
https://doi.org/10.1109/asic.1995.580724
https://doi.org/10.1109/asic.1995.580724
Publikováno v:
Proceedings of the Fourteenth Biennial University/Government/Industry Microelectronics Symposium (Cat. No.01CH37197).
Heuring and Jordan define a simplified, 32-bit RISC processor instruction set architecture called the simple RISC computer. An extended form of this architecture is defined, a gate-level logic design is developed, and a full-custom VLSI implementatio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a73f8823118afe83c820470b3ce7e728
https://doi.org/10.1109/ugim.2001.960330
https://doi.org/10.1109/ugim.2001.960330
Publikováno v:
HLDVT
The test problem increasingly affects system design costs. One approach for reducing testing difficulties is to consider system testability as early as possible in the design cycle. The technique described herein adds a testability analysis capabilit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6b37117df2c8b73182e64ca7999e1f74
https://doi.org/10.1109/hldvt.2000.889570
https://doi.org/10.1109/hldvt.2000.889570
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