Zobrazeno 1 - 10
of 62
pro vyhledávání: '"R.F. Hobson"'
Autor:
R.F. Hobson
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 15:173-181
A 6T static random access memory (SRAM) cell with a new write-assist (WA) feature is presented. The WA technique reduces the problem of writing a "one" through an nMOS pass device, thereby making a single-ended bit line more attractive. Both active p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::92dbfceabd86743ee22ebbba92384b55
https://doi.org/10.1109/tvlsi.2007.893580
https://doi.org/10.1109/tvlsi.2007.893580
Autor:
R.F. Hobson
Publikováno v:
IEEE Journal of Solid-State Circuits. 30:1020-1024
The regenerative carry based addition scheme has been found to be fast, area efficient, and power efficient. Previous work demonstrated the effectiveness of this technique compared with other fast adder techniques. This paper discusses optimization c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1469d470919136cb1924cda477174cc3
https://doi.org/10.1109/4.406402
https://doi.org/10.1109/4.406402
Autor:
R.F. Hobson, M.W. Fraser
Publikováno v:
IEEE Journal of Solid-State Circuits. 30:29-38
A new approach to integrating hardware multiplication, division, and square-root is presented. We use a fully integrated control path which simultaneously reduces part of the redundant partial-remainder and performs a truncated multiplication of the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4285ef49426a1423c9052b26ba78625a
https://doi.org/10.1109/4.350197
https://doi.org/10.1109/4.350197
Autor:
R.F. Hobson, D.J. Gamble
Publikováno v:
Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing.
New techniques for improving the productivity and working environment of designers who use procedural layout techniques for implementing VLSI module generators are described. APL and C, as examples of interpreted and compiled languages, can be interf
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7af4dbd45946ce3ef01843f43c3f697b
https://doi.org/10.1109/pacrim.1989.48437
https://doi.org/10.1109/pacrim.1989.48437
Autor:
R.F. Hobson, M. Rostam-Kafhesh
Publikováno v:
Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing.
A variation on the two-dimensional interconnection mesh is proposed which can be implemented very efficiently using VLSI technology for chips and packaging. Direct connectivity along rows and columns reduces the diagonal of an n*n 2-d mesh from 2n-2
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e6b37030fef12e170c1906b47ad93c47
https://doi.org/10.1109/pacrim.1989.48327
https://doi.org/10.1109/pacrim.1989.48327
Autor:
R.F. Hobson, Glenn H. Chapman
Publikováno v:
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration.
In both laser-link-oriented wafer scale integration (WSI) and multichip modules (MCMs), arrays of devices may be ordered in such a way that the actual physical position of devices is extremely important. Traditional graphic-based design systems are n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2e879e9f98eb5f533b23031edb5f39da
https://doi.org/10.1109/icwsi.1993.255264
https://doi.org/10.1109/icwsi.1993.255264
Autor:
R.F. Hobson
Publikováno v:
Great Lakes Symposium on VLSI
Power saving techniques for CMOS programmable logic arrays (PLAs) are discussed. Two new techniques are introduced, an AND-plane pulse generator, and wired-OR CMOS. Power reduction in excess of 75% over pseudo-NMOS techniques and 50% over some clocke
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2878185a449ba1482d1d62e9116d9256
https://doi.org/10.1109/glsv.1998.665196
https://doi.org/10.1109/glsv.1998.665196
Autor:
R.F. Hobson, P.S. Wong
Publikováno v:
IEEE WESCANEX 95. Communications, Power, and Computing. Conference Proceedings.
The asynchronous transfer mode segmentation and reassembly algorithm for adaptation layer 5 is broken down into concurrent tasks for efficient VLSI implementation.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::488e862586fce0a286289301b1569199
https://doi.org/10.1109/wescan.1995.493975
https://doi.org/10.1109/wescan.1995.493975
Publikováno v:
IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing. Proceedings.
We describe a 32-bit DRAM interface chip which controls 4 interleaved banks of standard commercial DRAMs with no additional glue chips. The chip performs transparent address translation on the column part of the address during the row access time. Ei
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0c9032476df0b77fb7bef2c1fd2c6a3a
https://doi.org/10.1109/pacrim.1995.519412
https://doi.org/10.1109/pacrim.1995.519412
Autor:
R. Balakrishnan, R.F. Hobson
Publikováno v:
Great Lakes Symposium on VLSI
Our objective was to integrate an effective channel routing algorithm with the Chip Design Language (CDL) algorithmic layout tool. CDL uses technology targetable layout techniques, so that the output of the routing algorithm can easily be ported to d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::569c2a0564cc014f9c4057036c6c855a
https://doi.org/10.1109/glsv.1999.757427
https://doi.org/10.1109/glsv.1999.757427