Zobrazeno 1 - 10
of 21
pro vyhledávání: '"R.A. Aroca"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 46:2226-2239
The design of a 60-Gb/s CMOS driver with input signal retiming is analyzed theoretically and validated experimentally. The output stage employs a modified distributed amplifier (DA) architecture with summation of both low-pass and reactively coupled
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b146db3b82c37eabd7fa6239643982a8
https://doi.org/10.1109/jssc.2011.2163214
https://doi.org/10.1109/jssc.2011.2163214
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:2085-2099
This paper presents a directly modulated, 60 GHz zero-IF transceiver architecture suitable for single-carrier, low-power, multi-gigabit wireless links in nanoscale CMOS technologies. This mm-wave front end architecture requires no upconversion of the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c8d9e167762a45a0f7021b2ad0991c50
https://doi.org/10.1109/jssc.2009.2022918
https://doi.org/10.1109/jssc.2009.2022918
Autor:
R.A. Aroca, Sorin P. Voinigescu
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:2177-2186
A fully differential 40-Gb/s cable driver with adjustable pre-emphasis is presented. The circuit is fabricated in a production 0.18 mum SiGe BiCMOS technology. A distributed limiting architecture is used for the driver employing high-speed HBTs in th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dbc09e3ddfc4dd17feb8a1fed0b5e8b3
https://doi.org/10.1109/jssc.2008.2002928
https://doi.org/10.1109/jssc.2008.2002928
Publikováno v:
IEEE Journal of Solid-State Circuits. 42:1564-1573
This paper presents low-voltage circuit topologies for 40-Gb/s communications in 90-nm and 65-nm CMOS. A retiming flip-flop implemented in two different 90-nm CMOS technologies employs a MOS-CML Master-Slave latch topology with only two vertically st
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::32b360f7959bd5ad57423547632dc765
https://doi.org/10.1109/jssc.2007.899093
https://doi.org/10.1109/jssc.2007.899093
Autor:
R.A. Aroca, C. Andre T. Salama
Publikováno v:
Analog Integrated Circuits and Signal Processing. 48:167-174
This paper presents the design and implementation of a new wide dynamic range parallel feedback (PF) transimpedance amplifier (TIA) for 10 Gb/s optical links. The wide dynamic range is attributed to the novel TIA architecture employing both shunt-shu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e64fc99c655e94d3c846b7c33f74dbb0
https://doi.org/10.1007/s10470-006-7631-x
https://doi.org/10.1007/s10470-006-7631-x
Publikováno v:
2010 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS).
A 60-Gb/s CMOS driver employing mm-wave DACs to achieve broadband waveshape control and pre-emphasis at different peaking frequencies is presented. It features a modified distributed amplifier (DA) architecture that achieves low-voltage and high- spe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b6d4ecd59bb01afba07922c175992793
https://doi.org/10.1109/csics.2010.5619605
https://doi.org/10.1109/csics.2010.5619605
Publikováno v:
CICC
This paper presents a 1.2 V 60 GHz zero-IF transceiver fabricated in a 65 nm CMOS process with a digital back-end. The chip includes a receiver with 14.7 dB gain, a low 5.6 dB noise figure, a 60 GHz LO distribution tree, a 64 GHz static frequency div
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7d3bad132e145da23f2c314adc99e9b2
https://doi.org/10.1109/cicc.2008.4672123
https://doi.org/10.1109/cicc.2008.4672123
Publikováno v:
2008 IEEE Symposium on VLSI Circuits.
The first 50-GHz to 110-GHz downconverter in 45-nm digital CMOS is presented along with the mm-wave characterization of AMOS varactors, inductors and transformers. The varactor Q is higher than 6, up to 94 GHz. The downconverter gain is 15 dB at 111G
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cfb0e0897c6b4bf0bdf130835e2185fb
https://doi.org/10.1109/vlsic.2008.4585991
https://doi.org/10.1109/vlsic.2008.4585991
Autor:
Timothy O. Dickson, Sorin P. Voinigescu, B. Sautreuil, C. Gamier, R.A. Aroca, T. Chalvatzis, Pascal Chevalier, S.T. Nicolson, P. Garcia
Publikováno v:
CICC
This paper describes first a half-rate, 2.5-V, 1.4-W, 87-Gb/s transmitter with on-chip PLL fabricated in a production 130-nm SiGe BiCMOS process. Next, the most critical blocks required for the implementation of a full-rate 100-Gb/s serial transceive
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aac31a2121b7283adb8f8c55a498e771
https://doi.org/10.1109/cicc.2007.4405776
https://doi.org/10.1109/cicc.2007.4405776
Publikováno v:
ICECS
This paper presents the first VLSI implementation of test circuitry for the continuous valued digits number system (CVNS). The CVNS is a recently introduced number system that uses a set of analog digits; the lower-order digits being used only to cor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::81cfd7fb3b342387f01fa12ab4727066
https://doi.org/10.1109/icecs.2002.1046187
https://doi.org/10.1109/icecs.2002.1046187