Zobrazeno 1 - 10
of 14
pro vyhledávání: '"R.-Ming Shiu"'
Publikováno v:
Journal of Systems and Software. 52:67-78
Branch target buffer (BTB) is widely used in modern microprocessor designs to reduce the penalties caused by branches. To evaluate the performance of a BTB, trace-driven simulation is often used. However, as the trace of a typical program is very lar
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2749456f818be7f43e50e2b4051a03d6
https://doi.org/10.1016/s0164-1212(99)00133-8
https://doi.org/10.1016/s0164-1212(99)00133-8
Publikováno v:
ICPADS
Register renaming eliminates storage conflicts for registers to allow more instruction level parallelism. This idea requires nontrivial implementation, however, especially when registers are accessible with different fields and data lengths. As a res
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::db2d211bccc21527234d5f8b3ea5970b
https://doi.org/10.1109/icpads.1996.517580
https://doi.org/10.1109/icpads.1996.517580
Publikováno v:
ICPADS
Because of register-memory instruction set architecture and limited register set, there are significant amounts of memory access instructions in x86 microprocessors. As the higher issue degree of superscalar microprocessor is provided, an aggressive
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::95ac090cf269a5fd0d7b4c264db34dd1
https://doi.org/10.1109/icpads.1998.741123
https://doi.org/10.1109/icpads.1998.741123
Publikováno v:
ICPADS
In the new generation of x86 microprocessors, superscalar techniques are used to achieve higher performance by executing multiple instructions in parallel. For compatibility and higher execution parallelism, the decoding units of these microprocessor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::96ee1a4236f60a6922bb83eb2357a0e5
https://doi.org/10.1109/icpads.1998.741119
https://doi.org/10.1109/icpads.1998.741119
Publikováno v:
ICPADS
Instruction cache prefetching is a technique to reduce the penalty caused by instruction cache misses. The prefetching methods generally determine the target line to be prefetched based on the current fetched line address. However, as the cache line
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::90103e938f2471fbaaec790d65211b7b
https://doi.org/10.1109/icpads.1997.652574
https://doi.org/10.1109/icpads.1997.652574
Autor:
R-Ming Shiu, 徐日明
88
In recent x86 microprocessors, superscalar techniques are widely used to achieve higher performance by executing multiple instructions in parallel. To exploit higher instruction level parallelism of current commercial programs on x86 supersca
In recent x86 microprocessors, superscalar techniques are widely used to achieve higher performance by executing multiple instructions in parallel. To exploit higher instruction level parallelism of current commercial programs on x86 supersca
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/29581566030543526466
Publikováno v:
Proceedings 1998 International Conference on Parallel & Distributed Systems (Cat No98TB100250); 1998, p496-503, 8p
Publikováno v:
Proceedings 1998 International Conference on Parallel & Distributed Systems (Cat No98TB100250); 1998, p488-495, 8p
Publikováno v:
Proceedings 1997 International Conference on Parallel & Distributed Systems; 1997, p360-365, 6p
Publikováno v:
Proceedings of 1996 International Conference on Parallel & Distributed Systems; 1996, p336-343, 8p