Zobrazeno 1 - 3
of 3
pro vyhledávání: '"R. Zh. Chochaev"'
Publikováno v:
Russian Microelectronics. 51:579-584
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e8bd2073866f8372a6adc165f7c536dc
https://doi.org/10.1134/s1063739722070046
https://doi.org/10.1134/s1063739722070046
Publikováno v:
Russian Microelectronics. 50:509-515
The problem of analyzing and evaluating the structure of FPGA routing resources at early stages of the design flow presents great interest for researchers. Until now, an approach, consisting in passing the full design flow (logic synthesis, placement
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6d0765ff83f10aebcc97b2f8a1194419
https://doi.org/10.1134/s1063739721070040
https://doi.org/10.1134/s1063739721070040
Autor:
V. I. Enns, S.V. Gavrilov, Mariya A. Zapletina, V.M. Khvatov, R. Zh. Chochaev, D. A. Zheleznikov
Publikováno v:
Russian Microelectronics. 48:176-186
A layout synthesis design flow for implementing designs on reconfigurable systems-on-chip is developed by the Institute for Design Problems in Microelectronics of Russian Academy of Sciences, in cooperation with JSC “NIIME” for special-purpose ci
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::54fb987d0f7ff1655835f53ee696f23d
https://doi.org/10.1134/s1063739719030053
https://doi.org/10.1134/s1063739719030053