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Autor:
Ah-Lyan Yee, A. Tsong, V. Pathak, Martin J. Izzard, E. Suder, J.M. Tran, R. Prentice, R. Venett, S. Spencer, R. Gu, Heng-Chih-Lin
Publikováno v:
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).
This paper describes a high speed, low jitter CMOS transceiver, which includes 10 to 1 full duplex serialize-deserialize function, clock recovery, high speed differential I/O, and Built In Self Test (BIST). It was fabricated and tested to work at wid
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::85947ad9fa86945340e03474262ce97d
https://doi.org/10.1109/vlsic.1999.797230
https://doi.org/10.1109/vlsic.1999.797230
