High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

Autor: P. Agnello, T. Ivers, C. Warm, R. Wise, R. Wachnik, D. Schepis, S. Sankaran, J. Norum, S. Luning, Y. Li, M. Khare, A. Grill, D. Edelstein, X. Chen, D. Brown, R. Augur, S. Wu, J. Yu, R.C. Wong, J. Werking, D. Wehella-Gamage, A. Vayshenker, H. Van Meer, R. Van Den Nieuwenhuizen, C. Tian, K. Tabakman, C.Y. Sung, T. Standaert, A. Simon, J. Sim, C. Sheraw, D. Restaino, W. Rausch, R. Pal, C. Prindle, X. Ouyang, C. Ouyang, V. Ontalus, K. Nummy, D. Nielsen, L. Nicholson, A. McKnight, N. Lustig, X. Liu, M.H. Lee, D. Lea, G. Larosa, W. Landers, B. Kim, M. Kelling, S.-J. Jeng, J. Holt, M. Hargrove, S. Grunow, S. Greco, S. Gates, A. Frye, P. Fisher, A. Domenicucci, C. Dimitrakopoulos, G. Costrini, A. Chou, J. Cheng, S. Butt, L. Black, M. Belyansky, I. Ahsan, T. Adam, A. Gabor, C.-H.J. Wu, D. Yang, M. Crouse, C. Robinson, D. Corliss, C. Fonseca, J. Johnson, M. Weybright, A. Waite, H.M. Nayfeh, K. Onishi, S. Narasimha

Publikováno v: 2006 International Electron Devices Meeting.

We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniq

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::bf10344b83d49f15325667340363c388
https://doi.org/10.1109/iedm.2006.346879