Zobrazeno 1 - 10
of 39
pro vyhledávání: '"R. Tawel"'
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 9:227-232
Evolvable hardware (EHW) addresses on-chip adaptation and self-configuration through evolutionary algorithms. Current programmable devices, in particular the analog ones, lack evolution-oriented characteristics. This paper proposes an evolution-orien
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f91adb0202dbbbf9fa3dff2948051139
https://doi.org/10.1109/92.920839
https://doi.org/10.1109/92.920839
Publikováno v:
IEEE Transactions on Industrial Electronics. 39:552-564
Time-critical neural network applications that require fully parallel hardware implementations for maximal throughput are considered. The rich array of technologies that are being pursued is surveyed, and the analog CMOS VLSI medium approach is focus
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f1c939a9ea322c5b0c731a9106b9712e
https://doi.org/10.1109/41.170975
https://doi.org/10.1109/41.170975
Publikováno v:
Evolvable Hardware
The paper describes the architectural details of a fine-grained programmable transistor array (PTA) architecture and illustrates its use in evolutionary experiments on the synthesis of both analog and digital circuits. A PTA chip was built in CMOS to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8571b7f41c9d55a1819c972d91a936ff
https://doi.org/10.1109/eh.1999.785437
https://doi.org/10.1109/eh.1999.785437
Publikováno v:
[Proceedings] 1992 RNNS/IEEE Symposium on Neuroinformatics and Neurocomputers.
Describes and analyses three different approaches to implementing a radial basis function neural network with an electronic neurocomputer. This type of network utilizes a radial basis function as the transfer function of the neuron. The three differe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3317dabdd36b5d863b28c0eda1adaa55
https://doi.org/10.1109/rnns.1992.268620
https://doi.org/10.1109/rnns.1992.268620
Autor:
R. Tawel
Publikováno v:
[Proceedings 1992] IJCNN International Joint Conference on Neural Networks.
A novel mathematical framework for the rapid learning of nonlinear mappings and topological transformations is presented. It is based on allowing the neuron's parameters to adapt as a function of learning. This fully recurrent adaptive neuron model h
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0d26ffc4610ffbce33a9c7a3f23b3da2
https://doi.org/10.1109/ijcnn.1992.227126
https://doi.org/10.1109/ijcnn.1992.227126
Publikováno v:
[Proceedings 1992] IJCNN International Joint Conference on Neural Networks.
An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::59fe8b155dcede8c2e600f82f9f87d7e
https://doi.org/10.1109/ijcnn.1992.226921
https://doi.org/10.1109/ijcnn.1992.226921
Autor:
R. Tawel
Publikováno v:
Data Compression Conference
A novel analog focal-plane processor, the Vector Array Processor (VAP), is designed specifically for use in real-time/video-rate on-line lossy image compression. This custom CMOS processor is based architecturally on the Vector Quantization algorithm
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::95aecf893a49c352729b6ac8b8e31ace
https://doi.org/10.1109/dcc.1993.253109
https://doi.org/10.1109/dcc.1993.253109
Publikováno v:
IJCNN-91-Seattle International Joint Conference on Neural Networks.
A competitive neural network architecture and hardware implementation is described. It is capable of solving first-order assignment problems. Each member of one set may be independently matched or blocked to a range of members of another set. One pro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d633a65336af5fcb684946b7fa03d7d6
https://doi.org/10.1109/ijcnn.1991.155215
https://doi.org/10.1109/ijcnn.1991.155215