Zobrazeno 1 - 10
of 26
pro vyhledávání: '"R. Rogenmoser"'
Autor:
Hubert Kaeslin, R. Rogenmoser
Publikováno v:
IEEE Journal of Solid-State Circuits. 32:1142-1145
Transistor size optimization is one method to reduce the power dissipation of CMOS very large scale integration (VLSI) circuits. Analysis shows that parasitic capacitances and velocity saturation of submicron technologies favor wider than minimum tra
Autor:
Qiuting Huang, R. Rogenmoser
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:401-409
An 8-b adder composed of carry-increment full adders has been designed and implemented in a standard 1.0 /spl mu/m CMOS technology and successfully tested up to 800 MHz. The performance of this adder is based on a fine-grain pipeline technique using
Autor:
Qiuting Huang, R. Rogenmoser
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:456-465
In digital circuits, a transistor connected to a particular circuit node does not always load that node by a gate capacitance proportional to C/sub ox/WL if the transistors connected to its source are turned off. Such an observation, illustrated in t
A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits
Autor:
J. Mitani, T. Bakhishev, Taiji Ema, Y. Liu, D. Zhao, M. Duane, Yasunobu Torii, Kazushi Fujita, Y. Asada, D. Kidd, H. Ahn, Mitsuaki Hori, Thomas Hoffmann, J. Nagayama, L. Scudder, S. Pradhan, L. T. Clark, R. Rogenmoser, P. Gregory, S. Lee, D. Kanai, M. Wojko, Scott E. Thompson, Lucian Shifren, Pushkar Ranade, E. Boling
Publikováno v:
2012 International Electron Devices Meeting.
65nm Deeply Depleted Channel (DDCTM) transistors have been fabricated with a halo-free, un-doped epitaxial channel and enable reduced threshold voltage (V T ) variation, lower supply voltage (V CC ), enhanced body effect and I EFF . Digital circuits
Autor:
R. Rogenmoser, S. Segars
Publikováno v:
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
Publikováno v:
Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.
The authors have designed a dual-modulus prescaler dividing either by 8 or 9 in a 1.2 /spl mu/m industrial CMOS process. With the use of advanced dynamic circuit techniques, a maximum frequency of 1.16 GHz has been reached at a supply of 5 V and 9 mA
Publikováno v:
Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.
We have implemented a dual-modulus prescaler dividing either by 64/65 (128/129) in a 1.2 /spl mu/m standard CMOS process. Using advanced dynamic circuit techniques a maximum frequency of 1.4 GHz has been measured at a supply of 5 V and 6.9 mA. An asy
Autor:
R. Rogenmoser, Qiuting Huang
Publikováno v:
Digest of Technical Papers., Symposium on VLSI Circuits..
A signed 8-bit pipelined multiplier has been implemented in a standard 1.0 /spl mu/m CMOS process. It was successfully tested up to 375 MHz. This performance was achieved using the true single-phase clocking technique, fine-grain pipelining, and merg
Autor:
Qiuting Huang, R. Rogenmoser
Publikováno v:
Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.
An 8-bit adder, operating at 800 MHz, and a single-stage bit-serial adder, running at more than 1 GHz, have been implemented and successfully tested in a standard 1.0 /spl mu/m CMOS process. The performance was achieved through the use of carry-incre
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.