Zobrazeno 1 - 10
of 111
pro vyhledávání: '"R. Rajsuman"'
Publikováno v:
IEEE Transactions on Instrumentation and Measurement. 54:1678-1698
To test next-generation system-on-a-chip (SoC) ICs, an open architecture automatic test equipment (ATE) has been conceived. Open architecture provides a framework to integrate software and instruments of different vendors into the ATE. The specificat
Autor:
R. Rajsuman
Publikováno v:
IEEE Design & Test of Computers. 18:16-27
Large on-chip memories are desirable but difficult to implement. Challenges range from design automation to fabrication to test algorithms and memory redundancy and repair.
Autor:
R. Rajsuman
Publikováno v:
Proceedings of the IEEE. 88:544-568
Autor:
R. Rajsuman, S.R. Das
Publikováno v:
IEEE Transactions on Instrumentation and Measurement. 55:378-380
Autor:
T.L. Anderson, Yervant Zorian, R. Rajsuman, R. Walther, C. Mallipeddi, Rajarathnam Chandramouli, Sujit Dey, S. Hemmady
Publikováno v:
IEEE Design & Test of Computers. 14:81-89
Autor:
R. Rajsuman, S. Hwang
Publikováno v:
VLSI Design. 5:299-311
In this paper, we examine the effectiveness of combined logic and IDDQ testing to detect stuck-at and bridging faults. The stuck-at faults are detected by the logic test and IDDQ testing detects bridging faults.Near minimal stuck-at test sets are use
Autor:
S.R. Das, R. Rajsuman
Publikováno v:
IEEE Transactions on Instrumentation and Measurement. 54:1659-1661
Publikováno v:
IEEE Journal of Solid-State Circuits. 30:855-863
Single BJT BiCMOS devices exhibit sequential behavior under transistor stuck-OPEN (s-OPEN) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-OPEN faults exhibiting sequential behavior needs two-pattern or m
Autor:
R. Rajsuman, Sunil R. Das
Publikováno v:
IEEE Transactions on Instrumentation and Measurement. 52:1350-1352
Autor:
R. Rajsuman
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 13:935-939
A testing method for EEPLA's is presented. The method requires small amount of extra hardware and provides complete fault coverage. This method exploits the fact that each crosspoint can be reprogrammed in EEPLA. To our knowledge, this is the first a