Zobrazeno 1 - 10
of 22
pro vyhledávání: '"R. Poorfard"'
Autor:
A. Maxim, R. Poorfard, M. Chennam, T. Nutt, Z. Dong, James Kao, David S. Trager, Richard A. Johnson, P. Crawley
Publikováno v:
IEEE Journal of Solid-State Circuits. 42:967-982
A low-IF fully integrated tuner for DBS satellite TV applications has been realized in 0.13-mum CMOS. A wideband ring oscillator-based frequency synthesizer having a large frequency step was used to downconvert a cluster of channels to a sliding low-
Autor:
T. Nutt, R. Poorfard, David S. Trager, Richard A. Johnson, Z. Dong, P. Crawley, A. Maxim, James Kao, M. Chennam, Mitchell Reid
Publikováno v:
IEEE Journal of Solid-State Circuits. 42:897-921
This paper presents the first low-IF fully integrated receiver for DBS satellite TV applications realized in 0.13 mum CMOS. A wideband ring oscillator based frequency synthesizer having a large frequency step was used to downconvert a cluster of chan
Publikováno v:
ISSCC
The proposed DDFS-driven mixing-DAC consists of several parallel-connected Gilbert cells driven directly by the binary and thermometer DDFS data compromise between power-dissipation and harmonic-rejection performance is achieved with 5b binary LSBs a
Publikováno v:
2008 IEEE Radio and Wireless Symposium.
A low-IF satellite TV demodulator front-end for single-chip receiver SoC was realized in 0.13 mum CMOS using a low-power 0.25mm2 8b time interleaved pipeline ADC. A 250MS/s conversion rate was achieved by sharing the sample-and-hold amplifier (SHA) b
Autor:
Z. Dong, A. Maxim, David S. Trager, M. Chennam, James Kao, P. Crawley, Richard A. Johnson, Mitchell Reid, R. Poorfard
Publikováno v:
2008 IEEE Radio and Wireless Symposium.
A digital low-IF receiver for satellite TV applications was realized in 110 nm CMOS taking advantage of high speed and moderate resolution ADCs and high digital processing power available in nanometer CMOS. A discrete gain step signal path and a digi
Publikováno v:
2007 IEEE Radio and Wireless Symposium.
A fully-integrated 0.13 μm CMOS ring oscillator based PLL for digital low-IF DVB-S/S2 satellite TV tuner is presented. An attenuator loop filter reduces the oscillator gain, helping both front-end noise and spur rejection, while a noiseless resistor
Autor:
James Kao, Z. Dong, M. Chennam, David S. Trager, Richard A. Johnson, R. Poorfard, A. Maxim, T. Nutt, P. Crawley
Publikováno v:
2007 IEEE Radio and Wireless Symposium.
A fully-integrated digital low-IF DVB-S/DVB-S2 satellite TV tuner was realized in 0.13 μm CMOS. It uses a first analog down-conversion to a sliding low-IF, followed by digitization, a second digital mixing to baseband and digital channel selection.
Autor:
M. Chennam, R. Poorfard, Z. Dong, P. Crawley, James Kao, David S. Trager, T. Nutt, Richard A. Johnson, A. Maxim
Publikováno v:
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..
A first low-IF fully-integrated tuner for DBS satellite TV applications was realized in 0.13 mum CMOS. A wide bandwidth, ring oscillator integer-N frequency synthesizer having a large frequency step was used to down-convert a cluster of channels to a
Autor:
Richard A. Johnson, M. Chennam, A. Maxim, David S. Trager, P. Crawley, T. Nutt, James Kao, R. Poorfard, Z. Dong
Publikováno v:
CICC
A digital low-IF fully-integrated dual tuner for DVB-S2 satellite TV applications was realized in 0.11 μm CMOS. It provides baseband digital I/Q outputs for a demodulator-on-host back-end processor. A wide bandwidth ring oscillator based frequency s
Autor:
M. Chennam, Richard A. Johnson, Z. Dong, T. Nutt, A. Maxim, P. Crawley, R. Poorfard, David S. Trager, James Kao
Publikováno v:
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006.
The first low-IF fully-integrated tuner for DBS satellite TV applications was realized in 0.13 /spl mu/m CMOS. A wideband ring oscillator based frequency synthesizer having a large frequency step was used to down-convert a cluster of channels to a co