Zobrazeno 1 - 10
of 28
pro vyhledávání: '"R. Jothin"'
Publikováno v:
Journal of Ambient Intelligence and Humanized Computing. 14:7219-7230
In the modern applications there are lot of computing resources starting from Central Processing Units, Networks on Chips to Field Programmable Gate Arrays, each catering various types of operations. These factors motivate this research, to exploit 1
Publikováno v:
Circuits, Systems, and Signal Processing. 40:4169-4185
This research article proposes high-performance square-root carry select adder (SQRT CSLA) architectures with high speed, area and energy efficiency when compared to the existing SQRT CSLA architectures. The first proposed method uses an optimized de
Autor:
M. Peer Mohamed, R. Jothin
Publikováno v:
Journal of Electronic Testing. 36:419-428
Efficient utilization of on-chip Static Random Access Memory (SRAM) space is more important on processor core design in modern Field Programmable Gate Array (FPGA) based Digital Signal Processing (DSP) applications. In the proposed High-performance A
Autor:
R. Jothin, C. Vasanthanayaki
Publikováno v:
Journal of Signal Processing Systems. 92:693-703
This research proposes a high-performance Carry Select Approximate Full Adder (CSAFA) with one error out of the eight possible output cases for high accuracy 8-bit pixel depth image processing applications. The logic optimization of the proposed CSAF
Autor:
C. Vasanthanayaki, R. Jothin
Publikováno v:
IETE Journal of Research. 67:205-216
In this paper, we proposed High Performance Error Tolerant Adders (HPETA) which have an efficient design and quality metrics for inexact computing applications. To achieve high performance, Multipl...
Autor:
R. Jothin, C. Vasanthanayaki
Publikováno v:
Journal of Electronic Testing. 34:607-614
Achieving high accuracy has become a key design objective in high quantity digital data computing devices. To enhance the accuracy, a high performance Modified Static Segment approximate Multiplier (MSSM) is proposed in this paper. It increases the a
Publikováno v:
Microelectronics Reliability. :1316-1321
Power gating technique is one of the most effective techniques to reduce the leakage power in complex arithmetic logic circuits. But this leakage power reduction technique induces some severe ground bouncing noise during mode transition. To mitigate
Autor:
C. Vasanthanayaki, R. Jothin
Publikováno v:
Journal of Electronic Testing. 34:389-404
The performance of the processor core depends on the configuration parameters and utilization of on-chip memory in multimedia applications such as image, video and audio processing. The design of the on-chip memory architecture is critical for power
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Autor:
C. Vasanthanayaki, R. Jothin
Publikováno v:
Journal of Electronic Testing. 33:125-132
Real time high quantity digital data computing design needs to achieve high performance with required accuracy range. The constraints involved with high performance are low power consumption, area efficiency and high speed. This paper proposes a desi