Zobrazeno 1 - 10
of 24
pro vyhledávání: '"R. Heussner"'
Autor:
V. Chikarmane, M. Hattendorf, S. Kosaraju, Abdur Rahman, M. Sprinkle, A. Tura, V. Sharma, G. Leatherman, H. Gomez, G. Ding, D. Towner, P. Sinha, C. Auth, S. Jaloviar, J. Birdsall, I. Post, B. Ho, D. Bergstrom, J. Leib, K. Lee, T. Mule, D. Hanken, M. Asoro, A. Saha, M. Sharma, C. Pelto, H. Meyer, M. Prince, L. Pipes, C. Staus, J. Shin, R. Heussner, S. Parthasarathy, C. Parker, V. Bhagwat, C. Ward, J. Dacuna Santos, M. Buehler, H. Hiramatsu, R. Suri, A. Aliyarukunju, M. Haran, S. Rajamani, A. Tripathi, P. Smith, A. Madhavan, W. Han, A. Yeoh, N. Bisnik, K. Marla, S. Joshi, H. Kothari, Q. Fu, I. Jin, S. Kirby, A. St. Amour
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local interconnect layers is described. For high density, a novel self-al
Autor:
K. Fischer, Pulkit Jain, Sell Bernhard, P. Plekhanov, Swaminathan Sivakumar, S. Rajamani, R. James, Mark Y. Liu, C. Kenyon, L. Neiberg, Pete Smith, J. Wiedemer, M. Haran, M. Prince, Kevin Zhang, A. Bowonder, S. Morarka, R. Mehandru, B. Song, M. Agostinelli, Q. Fu, Y. Luo, W. Han, M. Heckscher, R. Grover, R. Patel, V. Chikarmane, S. Akbar, S. Chouksey, P. Patel, D. Hanken, I. Jin, L. Pipes, C. Parker, J. Sandford, M. Giles, Paul A. Packan, Tahir Ghani, A. Paliwal, E. Haralson, M. Bost, K. Tone, Sanjay Natarajan, M. Yang, Eric Karl, Hei Kam, R. Jhaveri, R. Heussner, T. Troeger, A. Dasgupta, S. Govindaraju, C. Pelto
Publikováno v:
2014 IEEE International Electron Devices Meeting.
A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The
Publikováno v:
Applied Catalysis A: General. 199:53-60
The Bronsted-acid sites in several high-silica LTA samples were examined using temperature-programmed desorption (TPD) and thermogravimetric analysis (TGA) of alkylamines, as well as n-hexane cracking rates. Three samples were prepared with SiO2/Al2O
Autor:
Christopher D. Thomas, Michael L. Hattendorf, Mark R. Brazier, K. Zawadzki, R. McFadden, P. Hentges, J. Seiple, W. Han, D. Ingerly, S. Jaloviar, Cory E. Weber, Huichu Liu, Robert James, C. Auth, C. Parker, Kaizad Mistry, M. Prince, V. Chikarmane, S. Ramey, J. Neirynck, A. Blattner, J. Roesler, M. Bost, P. Yashar, D. Hanken, J. Jopling, Ian R. Post, B. McIntyre, C. Kenyon, T. Troeger, S. Pradhan, Pulkit Jain, D. Towner, C. Allen, David Jones, J. Hicks, Timothy E. Glassman, J. Sandford, L. Pipes, R. Heussner, T. Reynolds, M. Buehler, Daniel B. Bergstrom, Tahir Ghani, Pete Smith, R. Grover, Subhash M. Joshi
Publikováno v:
2012 Symposium on VLSI Technology (VLSIT).
A 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time. These transistors feature a 3rd-generation high-k + metal-gate technology and a 5th generation of channel strain techniques resultin
Autor:
J. Seiple, L. Neiberg, R. Heussner, W. Han, S. Lodha, Abhishek Sharma, T. Troeger, Paul A. Packan, Oleg Golonzka, Swaminathan Sivakumar, B. Mattis, Mark Armstrong, Daniel B. Bergstrom, Tahir Ghani, Kevin Zhang, K. Dev, Anand Portland Murthy, J. Neirynck, Jun He, C. Kenyon, Cory E. Weber, G. Ding, L. Pipes, H. Deshpande, S. Pae, Y. Luo, J. Jopling, A. St. Amour, Robert James, Mark Y. Liu, J. Sebastian, Sanjay Natarajan, B. Song, Sell Bernhard, S. Akbar, Mark R. Brazier, C. Parker, S-H. Lee, K. Tone
Publikováno v:
2009 IEEE International Electron Devices Meeting (IEDM).
A 32nm logic technology for high performance microprocessors is described. 2nd generation high-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for any 32nm or 28nm logic technology. NMOS drive currents are
Autor:
S. Lodha, J. Seiple, T. Troeger, S. Pae, G. Ding, Tahir Ghani, I. Jin, L. Pipes, C.-H. Chang, Ruth A. Brain, Cory E. Weber, Jun He, Kevin Zhang, Paul A. Packan, Robert James, R. Heussner, Seung Hwan Lee, S. Klopcic, W. Han, Anand Portland Murthy, Michael A. Childs, K. Dev, J. Neirynck, Mark Y. Liu, J. Sebastian, B. McFadden, Oleg Golonzka, Swaminathan Sivakumar, V. Chikarmane, C. Pelto, H. Deshpande, Sanjay Natarajan, Mark Armstrong, M. Yang, L. Neiberg, Mark R. Brazier, B. Song, Yeoh Andrew W, C. Parker, C. Kenyon, M. Bost, K. Tone, Sell Bernhard
Publikováno v:
2008 IEEE International Electron Devices Meeting.
A 32 nm generation logic technology is described incorporating 2nd-generation high-k + metal-gate technology, 193 nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9 Aring EOT hig
Publikováno v:
FIE '98. 28th Annual Frontiers in Education Conference. Moving from 'Teacher-Centered' to 'Learner-Centered' Education. Conference Proceedings (Cat. No.98CH36214).
Many creative and effective teaching strategies are forgotten or misplaced between semesters, only to be learned anew in subsequent semesters or lost forever. Beginning in September 1997, the University of Wisconsin-Madison College of Engineering lin
Autor:
Bruce Woolery, Swaminathan Sivakumar, C. Kenyon, Ramune Nagisetty, M. Bost, Cory E. Weber, P. Bai, Jack Hwang, T. Marieb, C. Auth, Kevin Zhang, Andrew Ott, Yeoh Andrew W, Sridhar Balakrishnan, D. Ingerly, C. Parker, J. Sebastian, Ruth A. Brain, Makarem A. Hussein, J. Neirynck, Anand Portland Murthy, Z. Ma, Seung Hwan Lee, Nick Lindert, Joseph M. Steigerwald, E. Lee, Mark Y. Liu, R. Shaheed, M. Bohr, R. Heussner, J. Jeong, V. Chikarmane, Sanjay Natarajan, R. James, S. Tyagi
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented. Transistor gate length is scaled down to 35n
Autor:
C. Kenyon, C. Auth, Mark Y. Liu, R. James, Swaminathan Sivakumar, H. Deshpande, S. Gannavaram, K. Tone, Sanjay Natarajan, C. Parker, Ramune Nagisetty, Nick Lindert, A. St. Amour, G. Curello, S. Tyagi, R. Heussner, J. Sebastian, P. Bai, Sell Bernhard, Oleg Golonzka, Seok-Hee Lee
Publikováno v:
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
An advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented. At 1V and off current of 100nA/mum, transistors have record currents of 1.21mA/mum and 0.71mA/mum for NMOS and PMOS respectivel
Autor:
R, Heussner
Publikováno v:
Minnesota medicine. 81(11)