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pro vyhledávání: '"R. Hallsall"'
Autor:
S. Jaroslawski, H.H. Wills, P. Shield, I.M. Silvester, G.P. Heath, R. Hallsall, S. Madani, M.A. Lancaster
Publikováno v:
IEEE Transactions on Nuclear Science. 37:1203-1207
The first-level trigger is a programmable 20-MHz pipelined machine based on user-programmable gate arrays, SRAMs (static random access memory) and other PLDs (programmable logic devices). The authors give an overview of the processor and concentrate