Zobrazeno 1 - 10
of 28
pro vyhledávání: '"R. El-Farhane"'
Publikováno v:
Solid State Phenomena. :37-40
This paper investigates low temperature cleaning steps solutions (T°
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6efd7e6b57f8f6e7cad6cebfef91998e
https://doi.org/10.4028/www.scientific.net/ssp.103-104.37
https://doi.org/10.4028/www.scientific.net/ssp.103-104.37
Autor:
T. Frank, Stephane Moreau, F. Lorut, P. Leduc, Lorena Anghel, R. El Farhane, Aurelie Thuaire, Lucile Arnaud, Cedrick Chappaz
Publikováno v:
Proc of IEEE International Reliability Physics Symposium (IRPS'11)
IEEE International Reliability Physics Symposium (IRPS'11), Monterey, CA, USA, April 10-14
IEEE International Reliability Physics Symposium (IRPS'11), Monterey, CA, USA, April 10-14, Apr 2011, Monterey, ca., United States. pp.3F.4.1-3F.4.6, ⟨10.1109/IRPS.2011.5784499⟩
IEEE International Reliability Physics Symposium (IRPS'11), Monterey, CA, USA, April 10-14
IEEE International Reliability Physics Symposium (IRPS'11), Monterey, CA, USA, April 10-14, Apr 2011, Monterey, ca., United States. pp.3F.4.1-3F.4.6, ⟨10.1109/IRPS.2011.5784499⟩
ISBN 978-1-4244-9111-7; International audience; 3D-IC integration using Through Silicon Via (TSV) is becoming an alternative to overcome obstacles of CMOS scaling. As TSV processes reach maturity, reliability investigation becomes critical. To the be
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c5cfa84aa873a0a96b0a85aa1a3e60f8
https://hal.archives-ouvertes.fr/hal-00599391
https://hal.archives-ouvertes.fr/hal-00599391
Autor:
Chaabouni, Henda, M., Rousseau, P., Leduc, A., Farcy, R. El, Farhane, A., Thuaire, G., Haury, A., Valentian, G., Billiot, M., Assous, F. De, Crecy, J., Cluzel, A., Toffoli, D., Bouchu, L., Cadix, T., Lacrevaz, P., Ancey, N., Sillon, B., Fléchet
Publikováno v:
IEEE International Electron Devices Meeting
IEEE International Electron Devices Meeting, Dec 2010, San Francisco, United States
IEEE International Electron Devices Meeting, Dec 2010, San Francisco, United States
International audience
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::48e5cd692a02f6a0933a9df32b360eb2
https://hal.archives-ouvertes.fr/hal-01074810
https://hal.archives-ouvertes.fr/hal-01074810
Autor:
R. El Farhane, Alain Toffoli, G. Haury, J. Cluzel, L. Cadix, P. Leduc, N. Sillon, D. Bouchu, Pascal Ancey, Aurelie Thuaire, Alexandre Valentian, H. Chaabouni, Maxime Rousseau, M. Assous, Bernard Flechet, F. de Crecy, G. Billiot, Thierry Lacrevaz, Alexis Farcy
Publikováno v:
IEEE International Electron Devices Meeting
IEEE International Electron Devices Meeting, Dec 2010, San Francisco, United States
IEEE International Electron Devices Meeting, Dec 2010, San Francisco, United States
4µm wide copper Through Silicon Vias (TSV) were processed on underlying 65nm CMOS devices and circuits in order to evaluate the impact of the three-dimensional (3D) integration process. Electrical tests on isolated MOSFET and ring oscillators in the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::87d7ca6e472fbe290ba5e00132c7db47
https://doi.org/10.1109/iedm.2010.5703479
https://doi.org/10.1109/iedm.2010.5703479
Autor:
R. Anciant, Cedric Bermond, C. Fuchs, J.-L. Huguenin, Alexis Farcy, R. El Farhane, Maxime Rousseau, P. Leduc, N. Sillon, Perceval Coudrain, H. Chaabouni, Lionel Cadix, Aurelie Thuaire, Bernard Flechet, Pascal Ancey
Publikováno v:
IEEE International Interconnect Technology Conference
IEEE International Interconnect Technology Conference, Jun 2010, San Francisco, United States
IEEE International Interconnect Technology Conference, Jun 2010, San Francisco, United States
Evaluation of Through Silicon Via (TSV) electrical parameters is mandatory to improve heterogeneous 3D chip performance in the frame of a “more than Moore” roadmap. Accurate modeling of TSV is consequently essential to perform design, material an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f6943c2311660a324ec74ae0239c4d1b
https://hal.archives-ouvertes.fr/hal-00604331
https://hal.archives-ouvertes.fr/hal-00604331
Autor:
C. Rossato, N. Casanova, B. Dumont, Simone Pokrant, A. Pouydebasque, D. Lenoblet, A. Halimaouit, Thomas Skotnicki, C. Laviron, V. Carron, R. El-Farhane
Publikováno v:
Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005..
In this work, we report a study of the integration of NMOS and PMOS junctions with solid phase epitaxy (SPE). For the first time, considerably improved short channel effects are demonstrated with SPE for both NMOS and PMOS (-30% / -25% in DIBL at L/s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::590aaa029b3088b2067271bf55c73dde
https://doi.org/10.1109/essder.2005.1546674
https://doi.org/10.1109/essder.2005.1546674
Autor:
J. Todeschini, M. Bidaud, J. Rosa, H. Bernard, Franck Arnaud, M. Jurdit, D. Sotta, B. Duriez, J. Grant, Laurent Pain, Thomas Skotnicki, N. Bicais-Lepinay, Pierre Morin, J. Bustos, C. Chaton, Francois Wacquant, R. El-Farhane, Frederic Boeuf, Pascal Gouraud, M.T. Basso, S. Manakli, S. Jullian, V. DeJonghe, B. Tavel, M. Gaillardin
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
In this work, a low-cost 45nm node platform for general purpose and low power applications based on conventional bulk approach is proposed. Performant Lg=30nm/45nm devices with SiON gate oxide, shallow junctions and process induced strain are demonst
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6b0c59f4f0efd04c243db59f149ec997
https://doi.org/10.1109/iedm.2004.1419177
https://doi.org/10.1109/iedm.2004.1419177
Autor:
R. El-Farhane, Simone Pokrant, C. Laviron, B. Dumont, Damien Lenoble, Frederic Boeuf, A. Pouydebasque, Franck Arnaud, Thomas Skotnicki, A. Dray, V. Carron, B. Duriez, F. Salvetti, Aomar Halimaoui, Francois Wacquant, C. Rossato
Publikováno v:
Extended Abstracts of the Fifth International Workshop on Junction Technology.
This paper demonstrates that, for NMOS, the use of LSA and smart junction engineering enable to improve dramatically short channel effects (-65% in DIBL at L/sub g/=45 nm due to lower X/sub j/ and DL) and I/sub on//I/sub off/ performance (+7% I/sub o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bcac50bc5ec71778bc56c13828aa5bb2
https://doi.org/10.1109/iwjt.2005.203867
https://doi.org/10.1109/iwjt.2005.203867
Autor:
Pierre Morin, A. Pouydebasque, Franck Arnaud, T. Skotnicki, D. Bensahel, A. Halimaoui, C. Laviron, R. El Farhane, P. Stolk, Frederic Boeuf
Publikováno v:
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).
We demonstrate in this paper the viability of an ultra-low thermal budget CMOS process enabling the formation of ultra shallow junctions with competitive transistor characteristics. In particular, it is shown that the use of self-amorphizing implants
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::711ee4e5936fd979bca5f555faee4de2
https://doi.org/10.1109/essder.2004.1356507
https://doi.org/10.1109/essder.2004.1356507