Zobrazeno 1 - 10
of 31
pro vyhledávání: '"R. Difrenza"'
Autor:
L. Vishnubhotla, Pierre Morin, Robert Fox, S. Boret, R. Difrenza, B. Tavel, K. Rochereau, P. Stolk, C. Detcheverry, Daniel Gloria, M.T. Basso, M. Woo, M. Broekaart, B. Duriez, P. Garnier, D. Reber, Y. Trouille, J. Bienacel, M. Denais, D. Barge, C. Ortolland, K. Cooper, Frederic Boeuf, S. Vanbergue, Vincent Huard, Jean-Damien Chapon, J. Belledent, Pascal Gouraud, Nicolas Planes, Franck Arnaud, P. Abramowitz, E. Saboure, Y. Laplanche, C. Julien, M. Bidaud, M. Marin, Romain Gwoziecki
Publikováno v:
Solid-State Electronics. 50:573-578
A complete 65 nm CMOS platform, called LP/GP Mix, has been developed employing thick oxide transistor (IO), Low Power (LP) and General Purpose (GP) devices on the same chip. Dedicated to wireless multi-media and consumer applications, this new triple
Publikováno v:
Solid-State Electronics. 47:1167-1171
This paper presents a new model for the current factor mismatch of the MOS transistor. It demonstrates that the impact of interface states is negligible. Therefore, the analytical model is based on the random variations of the dopant number in the ch
Publikováno v:
Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, 2005..
Matching of bipolar transistors has been characterized for high currents. The predominant impact of access resistance mismatch is clearly demonstrated, and matching models are suggested. Moreover, matching results dependency on test configurations is
Autor:
K. Rochereau, P. Stolk, S. Jullian, David Roy, Alessandro Dezzani, B. Duriez, T. Devoivre, Franck Arnaud, R. Boulestin, B. Tavel, R. Difrenza
Publikováno v:
Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005..
The 65 nm process has been optimized through thermal budget and implant of halo and LDD to reduce gate impact. It provides the best matching results ever reported to our knowledge, i.e. A/sub Vt/ of 2.1 and 1.9 mV./spl mu/m for NMOS and PMOS respecti
Autor:
R. Difrenza, P. Stolk, M. Bidaud, Pierre Morin, M. Woo, B. Tavel, R. Wacquant, M. Denais, Franck Arnaud, R. Boeuf, F. Payet, D. Reber, N. Cagnat, K. Rochereau, M. Marin, M.T. Basso, B. Duriez, C. Ortolland, Damien Lenoble, Y. Laplanche, C. Dachs, H. Brut, David Roy, R. Palla, D. Barge
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
This paper demonstrates a full gate stack optimization by using post gate anneal (PGA) solution coupled with both germanium and fluorine gate predoping. We obtained a large carrier mobility enhancement for both NMOS (+50%) and PMOS (+20%) thanks to a
Autor:
M. Denais, B. Tavel, B. Froment, K. Rochereau, P. Stolk, Franck Arnaud, B. Duriez, Pierre Morin, R. Difrenza, Pascal Gouraud, A. Margin, David Roy, M. Woo, M. Bidaud
Publikováno v:
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).
In this work, a complete low temperature 65 nm process flow using a low-cost, conventional CMOS approach has been investigated. A significant global thermal budget reduction has been achieved (below 500/spl deg/C), especially for the spacer, silicide
Publikováno v:
Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516).
This paper deals with MOS transistors mismatch for advanced 120 nm and 90 nm CMOS technologies. In particular we demonstrate pocket implant impact on the gate contribution that becomes more and more important with the gate oxide thickness reduction.
Autor:
Nathalie Revil, N. Emonet, P. Llinares, R. Difrenza, M. Denais, Roland Pantel, M. Woo, Vincent Huard, Kathy Barla, J. C. Vildeuil, H. Brut, C. Parthasarthy, M. Bidaud, P. Stolk, Franck Arnaud, David Roy, F. Guyader, K. Rochereau, L. Vishnubotla, D. Barge, Nicolas Planes, Sylvie Bruyere, B. Tavel
Publikováno v:
IEEE International Electron Devices Meeting 2003.
This work shows the benefits of using plasma nitrided gate oxide which supports the gate leakage requirements for 65 nm platform development. Electrical data shows gate leakage to be reduced by half a decade compared to conventional NO processing wit
Autor:
M. Denais, J. Todeschini, R.A. Bianchi, Damien Lenoble, Laurent Pain, Y. Laplanche, Franck Arnaud, H. Brut, M. Broekaart, Nicolas Planes, V. Vachellerie, M. Woo, A. Beverina, Pierre Morin, R. Difrenza, Bertrand Borot, C. Perrot, H. Leninger, Francois Wacquant, D. Barge, David Roy, F. Salvetti, D. Ceccarelli, N. Emonet, V. DeJonghe, P. Stolk, B. Tavel, B. Duriez, L. Vishnobulta, I. Guilmeau, Y. Loquet, Frederic Boeuf, T. Devoivre, N. Bicais, J.P. Reynard, M. Jurdit, K. Rochereau, R. Palla, F. Judong, M. Bidaud, P. Vannier, D. Reber
Publikováno v:
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..
A 65nm CMOS platform employing General Purpose (GP) and Low Power (LP) devices and 0.5 /spl mu/m/sup 2/ 6T-SRAM bit-cells was developed using both conventional design and low cost CMOS process flow incorporating a strained silicon solution. Fully wor
Publikováno v:
International Conference on Microelectronic Test Structures, 2003..
This paper presents a compact model for the gate impact on MOS transistor matching. It is based on the random variations of grain number in the polycrystalline gate. The model is validated by fitting mismatch increase with substrate bias. This study