Zobrazeno 1 - 10
of 44
pro vyhledávání: '"R. Cuppens"'
Autor:
Michiel Slotboom, N. Akil, P. Goarin, R. van Schaijk, M.J. van Duuren, W. Baks, P.G. Tello, R. Cuppens
Publikováno v:
IEEE Transactions on Electron Devices. 52:492-499
The performance of compact nonvolatile memory cells, meant for embedded applications in advanced CMOS processes, is studied and analyzed in detail by means of technology computer-aided design (TCAD), and new experimental results are presented. Improv
Publikováno v:
Microelectronic Engineering. 22:53-60
In this paper an overview will be given of the field of non-volatile ferroelectric memories with the emphasis on material and processing aspects for high density applications. The emerging field of high permittivity dielectric materials for dynamic r
Publikováno v:
Microelectronic Engineering. 19:245-252
In the late 1980s the interest in ferroelectric materials for memory applications has been renewed on the basis of concepts where ferroelectric thin film capacitors are embedded in Integrated Circuit processes. This paper discusses the application of
Publikováno v:
Ferroelectrics. 128:265-292
Autor:
K. Smith, C. Frey, B. Feil, T. Ditewig, J. J. Sun, J. Chan, R. Fournel, R. Cuppens, Mark A. Durlam, D. Galpin, L. Wise, Saied N. Tehrani, M. Lien, Mark F. Deherrera, J. Tamim, Thomas W. Andre, J. Calder, Gloria Kerszykowski, Joseph J. Nahas, K. Nagel, R. Williams, B. Martino, Bradley J. Garni, S. Zoll, Jason Allen Janesky, Chitra K. Subramanian, J. Martin, Renu W. Dave, F. List, B.N. Engel, P. Brown, G. Grynkewich
Publikováno v:
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
A 90nm magnetoresistive random access memory (MRAM) based on the toggle switching mode has been successfully demonstrated for the first time in a 90nm CMOS process. The MRAM memory cell is based on a 1-transistor 1-magnetic tunnel junction (1T1MTJ) w
Publikováno v:
International Technical Digest on Electron Devices Meeting.
A single polysilicon CMOS process optimized for the production of nonvolatile memory embedded in VLSI logic is described. The process differs from conventional approaches in two aspects: it uses a TiSi/sub 2/ control gate instead of a thicker polysil
Autor:
F. Jetten, T. Ditewig, M. Storms, R. Cuppens, Kuo-Lung Chen, N. Tandan, W. Kalkman, M. Malabry, A. Slenter, J. Gracio, V. Frowijn, S. Teuben
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
An embedded flash memory module has 1.2 V read capability and a 1.5 V program/erase capability. The flash cell is 2-transistor FN-NOR in a 0.181 /spl mu/m logic process. Design techniques improve observability and reduce test time.
Publikováno v:
Science and Technology of Electroceramic Thin Films ISBN: 9789048145140
Science and Technology of Electroceramic Thin Films
Science and Technology of Electroceramic Thin Films
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6b3eed5c68af8bafcc960e3b429b745c
https://doi.org/10.1007/978-94-017-2950-5_15
https://doi.org/10.1007/978-94-017-2950-5_15
Publikováno v:
IEEE Journal of Solid-State Circuits. 12:217-222
Using a compatible silicon-gate p-MOS-bipolar technology (SIGBIP), a voltage follower is described with protected MOSFET input stage featuring less than 1-pA input current, less than 0.1-pF input capacitance, 10-MHz bandwidth, 20-/spl mu/V p-t-p nois
Publikováno v:
IEEE Journal of Solid-State Circuits. 14:543-547
A circuit configuration to simulate large on-chip capacitors and inductors is discussed. It is based on the backward-Euler integration rule and can be realized by means of a sample-and-hold function. It leads to filters with time constants determined