Zobrazeno 1 - 10
of 37
pro vyhledávání: '"R. Cleavelin"'
Autor:
Klaus Schruefer, Brian Clappin, Thomas Schulz, Kara Sherman, Koki Mochizuki, Wei Ze Xiong, R. Cleavelin, Hu Cheng Lee, Jeffrey M. Lauerhaas
Publikováno v:
Solid State Phenomena. 134:213-216
Autor:
Sanjay K. Banerjee, M. Freeman, Rick L. Wise, Angelo Pinto, Yao-Tsung Huang, Chien-Ting Lin, M. Ramin, B. Wilks, L. Denning, R. Cleavelin, M. Ma, J. Bennet, B. Nguyen, C. Johnson, K. Matthews, Mike Seacrist, M. Ries, S. Joshi
Publikováno v:
IEEE Transactions on Electron Devices. 54:2045-2050
Direct silicon bonding (DSB) for hybrid orientation technology has recently generated a lot of interest due to the significant performance enhancements reported for PMOS devices that are fabricated on alternative substrate orientations. Significantly
Autor:
M. Gostkowski, T. Schulz, J.R. Zaman, A. Vazquez, Ken Matthews, Jean-Pierre Colinge, Weize Xiong, James M. Frei, Chad Johns, Nirmal Chaudhary, C. R. Cleavelin, G. Gebara
Publikováno v:
IEEE Electron Device Letters. 25:813-815
A simple model based on the representation of capacitive coupling effects between the front- and back-gate and the channels, has been developed for tri-gate and pi-gate SOI MOSFETs. The model has been validated using numerical simulation of the body
Publikováno v:
IEEE Conference Proceedings CFP 09CAS-PRT
International Semiconductor Conference
International Semiconductor Conference, Oct 2009, Sinaia, Romania. pp.51-56
International Semiconductor Conference
International Semiconductor Conference, Oct 2009, Sinaia, Romania. pp.51-56
The typical electrical properties of triple-gate SOI MOSFETs are investigated. The relationship between the short-channel effect (SCE) and the inter-gate coupling effect is studied as a function of the channel length and width. The three-dimensional
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0132197f78025ed9a0c1e8ef7bd029cb
https://hal.archives-ouvertes.fr/hal-00603672
https://hal.archives-ouvertes.fr/hal-00603672
Publikováno v:
Nanoscaled Semiconductor-on-Insulator Structures and Devices ISBN: 9781402063787
In order to evaluate the impact of the presence of individual doping atoms in a trigate MOSFET, three-dimensional simulations were carried out. The Poisson equation is solved numerically in the channel of the devices numerically using Comsol Multiphy
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::efd3e69dad1782dddd9772e54f59699c
https://doi.org/10.1007/978-1-4020-6380-0_12
https://doi.org/10.1007/978-1-4020-6380-0_12
Autor:
Weize Xiong, T. Schulz, Wolfgang Molzer, Jean-Pierre Colinge, P. Patruno, K. Schrufer, G. Knoblinger, Domagoj Siprak, R. Cleavelin, J. Sedlmeir, L. Bertolissi, Ken Matthews, Andrew Marshall
Publikováno v:
2006 European Solid-State Device Research Conference.
Due to material properties and geometric aspects self heating simulation of silicon devices requires 3D simulation of large structures. Fully coupled electrothermal simulation in three spatial dimensions is extremely memory and CPU time intensive. Th
Autor:
M. Kerber, W. Xiong, Joe W. McPherson, G.S. Haase, E.T. Ogawa, T. Pompl, K. Schrufer, T. Schulz, Homi C. Mogul, R. Cleavelin
Publikováno v:
2006 IEEE International Reliability Physics Symposium Proceedings.
Future CMOS technology generations may implement multi-gate architectures according to S. M. Kim et al. (2004), D Ha et al. (2004), S.-Y. Kim et al. (2005), W.-S. Liao et al. (2005), S. Maeda et al. (2004), N. Collaert et al. (2005),and C. Jahan et a
Autor:
Weize Xiong, M. Gostkowski, T. Schulz, Charvaka Duvvury, P. Patruno, Klaus Schruefer, Harald Gossner, C. Russ, Jörg Berthold, Christian Pacha, Andrew Marshall, Thomas Nirschl, K. von Arnim, R. Cleavelin, G. Knoblinger
Publikováno v:
ISSCC
Scopus-Elsevier
Scopus-Elsevier
Multi-gate FETs are promising for sub-45nm CMOS technologies. To address the link between design and technology, basic digital and analog circuits are fabricated using FinFET and triple-gate FETs. Digital circuit performance, leakage currents, and po
Publikováno v:
2004 IEEE International Reliability Physics Symposium. Proceedings.
As the challenges to conventional scaling become more difficult, strained Si/relaxed Si/sub 1-x/Ge/sub x/ structures provide a viable means of improving CMOS performance. For NMOSFETs, the tensile strain in pseudomorphic Si on relaxed Si/sub 1-x/Ge/s
Autor:
R. Cleavelin
Publikováno v:
10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295).
Summary form only given. The 1999 International Technology Roadmap for Semiconductors (ITRS) is currently being developed and is scheduled for release in November 1999. Key to this roadmap is the evolutionary development of manufacturable front-end p