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Modelling The Effects Of Instruction Queue Loading On A Static Instruction Stream Micro-architecture
Publikováno v:
[1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21.
Increased processor performance requires the exploitation of the parallelism that exists within the instruction stream and within the processor itself: A static instruction stream micro-architecture, CONDEL, extracts and uses the machine instruction
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fabaa986ff206aa4b29a977327345c54
https://doi.org/10.1109/micro.1988.639239
https://doi.org/10.1109/micro.1988.639239
