Zobrazeno 1 - 10
of 48
pro vyhledávání: '"R. Anciant"'
Publikováno v:
Journal of Electronic Materials. 43:685-694
Chip-to-wafer stacking is a key enabling technology for two and half dimension (2.5D) as well as for three dimension (3D), with technological challenges driven by the increase of the die surface and the number of input/outputs (I/Os) and the reductio
Publikováno v:
Journal of Microelectromechanical Systems. 22:303-308
This paper analyzes the bias sources of mechanical and electrostatic origin in a tuning fork microelectromechanical systems (MEMS) gyroscope. In a gyroscope which is symmetrical and has no defect, there would be no bias; technological defects should
Autor:
F. Schnegg, C. Karoui, G. Klug, Gilles Simon, H. Luesebrink, R. Anciant, K. Martinschitz, A. Attard, G. Parès, F. De Crecy, A. N'hari, D. Cruau
Publikováno v:
International Symposium on Microelectronics. 2012:000710-000719
Chip-to-wafer stacking is a key enabling technology for 2.5D as well as for 3D with technological challenges driven by on one hand the increase of the die surface and the number of I/Os and on the other hand by the reduction of the vertical dimension
Autor:
M. Volpert, Frédéric Berger, François Marion, R. Anciant, B. Goubault de Brugiere, H. Ribot, Alain Gueugnot, Alexis Bedoin
Publikováno v:
2013 IEEE 63rd Electronic Components and Technology Conference.
In this work we show that high density and very low pitches face to face Aluminum/Aluminum cold bonding is feasible when using Aluminum coated micro-tubes inserted into Aluminum pads. First, mechanical simulations by FEM show that the insertion press
Publikováno v:
2013 IEEE 63rd Electronic Components and Technology Conference.
Copper tin transient liquid phase bonding reliability was investigated with different setups including CuSn to Cu and CuSn to CuSn bonding. Additionally, a thermal treatment just after CuSn electrodeposition (ECD) was compared to the classical config
Autor:
P. Leduc, J-C. Marin, Cedric Bermond, Thierry Lacrevaz, M. Brocard, N. Sillon, S. Cheramy, H. Ben Jamaa, Alexis Farcy, Bernard Flechet, P. Le Maitre, N. Hotellier, Pierre Bar, R. Anciant, Perceval Coudrain
Publikováno v:
2012 IEEE 62nd Electronic Components and Technology Conference.
TSVs in 3D integrated circuits are a source of noise that can affect nearby transistor performance. So an analytical physics-based model of the TSV-to-substrate coupling is proposed to perform time domain or noise simulations. Silicon measurements at
Autor:
Sébastien Bolis, Claudine Bridoux, Fabrice Jacquet, A. Pouydebasque, Damien Saint-Patrice, R. Anciant, Emmanuelle Vigier-Blanc, N. Sillon
Publikováno v:
2011 IEEE 61st Electronic Components and Technology Conference (ECTC).
Devices for consumers like camera phones are essentially driven by the cost and performances. In that scope, several new key technologies are requested to achieve a complete active waferlevel camera (with autofocus or zoom). A low cost vias interconn
Autor:
Severine Cheramy, J. Charbonnier, C. Fuchs, Alexis Farcy, G. Garnier, C. Brunet-Manquat, J. Diaz, O. Hajji, R. Anciant, Pascal Ancey, D. Henry, P. Vincent, Lionel Cadix, N. Sillon, P. Chausse
Publikováno v:
2011 IEEE International Interconnect Technology Conference.
In this paper, high density TSV integration in silicon interposer is presented, fully characterized and simulated (DC and RF). Parasitic elements of the RF model are extracted. Dielectric and metal process improvements are developed and their impact
Autor:
R. Anciant, N. Sillon, N. Bresson, P. Brianceau, J. F. Lugand, G. Pares, S. Minoret, V. Lapras
Publikováno v:
2011 IEEE International Conference on IC Design & Technology.
Through Silicon Vias (TSV) is a very promising technology in advanced packaging, for the replacement of wire bonding. This technology is becoming mandatory for fully integrated products such as SiP, SoP, 3D components integration (e.g memory stacking
Autor:
R. Anciant, Cedric Bermond, C. Fuchs, J.-L. Huguenin, Alexis Farcy, R. El Farhane, Maxime Rousseau, P. Leduc, N. Sillon, Perceval Coudrain, H. Chaabouni, Lionel Cadix, Aurelie Thuaire, Bernard Flechet, Pascal Ancey
Publikováno v:
IEEE International Interconnect Technology Conference
IEEE International Interconnect Technology Conference, Jun 2010, San Francisco, United States
IEEE International Interconnect Technology Conference, Jun 2010, San Francisco, United States
Evaluation of Through Silicon Via (TSV) electrical parameters is mandatory to improve heterogeneous 3D chip performance in the frame of a “more than Moore” roadmap. Accurate modeling of TSV is consequently essential to perform design, material an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f6943c2311660a324ec74ae0239c4d1b
https://hal.archives-ouvertes.fr/hal-00604331
https://hal.archives-ouvertes.fr/hal-00604331