Zobrazeno 1 - 10
of 39
pro vyhledávání: '"R R Manikandan"'
Autor:
Vinod Menezes, R R Manikandan, Mahesh Mehendale, Raveesh Magod, Rajat Chauhan, Anantha P. Chandrakasan, Vipul Singhal
Publikováno v:
VLSI Design
Power management systems for wireless sensor nodes in industrial IoT applications need to operate seamlessly from multiple energy sources and efficiently manage power delivery to multiple load circuits. This paper presents a single chip integrated po
Publikováno v:
VLSI Design
An ultra-low energy KHz timer/oscillator circuit suitable for heavily duty cycled systems is presented. The proposed oscillator design utilizes a 3-stage ring topology made of CMOS Schmitt trigger delay cells biased with sub-nA currents. To extract a
Autor:
R. R. Manikandan, Bharadwaj Amrutur
Publikováno v:
Microelectronics Journal. 46:422-430
The charge-pump (CP) mismatch current is a dominant source of static phase error and reference spur in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect. This paper presents a charge-pump (CP) mismatch curre
Publikováno v:
VLSI Design
A switchable number of turns, symmetric, parallel stacked, variable width and spacing inductor structure with performance optimized for multi-band operation and an area efficient multi-band voltage controlled oscillator circuit (VCO) are presented. T
Autor:
Bharadwaj Amrutur, R. R. Manikandan
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 60:852-856
In this brief, the substrate noise effects of a pulsed clocking scheme on the output spur level, the phase noise, and the peak-to-peak (Pk-Pk) deterministic period jitter of an integer-N charge-pump phase-locked loop (PLL) are demonstrated experiment
Publikováno v:
IndraStra Global.
A logic gate-based digital frequency multiplication technique for low-power frequency synthesis is presented. The proposed digital edge combining approach offers broadband operation with low-power and low-area advantages and is a promising candidate
Publikováno v:
2014 IEEE International Microwave and RF Conference (IMaRC).
The on-chip planar spiral inductors having variable width (W) and spacing (S) across their turns are known to exhibit higher quality factors (Q). In this paper, we present an efficient parameterized cell (pcell) design in cadence using SKILL scripts
Publikováno v:
VDAT
Layout optimized planar spiral inductors using variable width (W) and spacing (S) across their turns are known to exhibit higher quality factors (Q). In this paper, we explore the performance improvement of 3-dimensional, series-stacked, parallel-sta
Autor:
Sibmah, S.1 sibmah1998@gmail.com, Kirupavasam, E. K.1
Publikováno v:
Indian Journal of Chemistry (0019-5103). 2022, Vol. 61 Issue 8, p901-908. 8p.
Autor:
Triveni, Cherukuri1 cherukuri.triveni1357@gmail.com, Vani, K. Suvarna1 suvarnavanik@vrsiddhartha.ac.in, Likhitha, M.1 likhithamorla9@gmail.com
Publikováno v:
Journal of Information Technology Management (JITM). 2023 Special Issue, Vol. 15, p102-119. 18p.