Zobrazeno 1 - 10
of 52
pro vyhledávání: '"R Berthelon"'
Autor:
A. Redaelli, A. Gandolfo, G. Samanni, E. Gomiero, E. Petroni, L. Scotti, A. Lippiello, P. Mattavelli, J. Jasse, D. Codegoni, A. Serafini, R. Ranica, C. Boccaccio, J. Sandrini, R. Berthelon, J.-C. Grenier, O. Weber, D. Turgis, A. Valery, S. Del Medico, V. Caubet, J.-P. Reynard, D. Dutartre, L. Favennec, A. Conte, F. Disegni, M. De Tomasi, A. Ventre, M. Baldo, D. Ielmini, A. Maurelli, P. Ferreira, F. Arnaud, F. Piazza, P. Cappelletti, R. Annunziata, R. Gonella
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 10, Pp 563-568 (2022)
The effect of back-end of line (BEOL) process on cell performance and reliability of Phase-Change Memory embedded in a 28nm FD-SOI platform (ePCM) is discussed. The microscopic evolution of the Ge-rich GST alloy during process is the focus of the fir
Externí odkaz:
https://doaj.org/article/c2fbeb39b1c14d23a0f92983e7149df3
Autor:
E. Gomiero, G. Samanni, J. Jasse, C. Jahan, O. Weber, R. Berthelon, R. Ranica, L. Favennec, V. Caubet, D. Ristoiu, J. P. Reynard, L. Clement, P. Zuliani, R. Annunziata, F. Arnaud
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 7, Pp 517-521 (2019)
Quenching-time characterization is the way to measure the speed of chalcogenide material to transform from the amorphous (RESET) state to the crystalline (SET) one after application of a proper programming pulse. It is here proposed to study the impa
Externí odkaz:
https://doaj.org/article/d32a756f1cf8471fafe70bc493d62c3c
Autor:
Xinke Wang, Xiao Gong, Jie Liang, R. Berthelon, Christophe Maleville, Franck Arnaud, Aaron Thean, Haiwen Xu, Bich-Yen Nguyen, Olivier Weber, Eugene Y.-J. Kong, Chen Sun, Walter Schwarzenbach
Publikováno v:
IEEE Transactions on Electron Devices. 68:1425-1431
The relaxation of tensile strain in fully depleted (FD) strained silicon-on-insulator (SSOI) by means of ion implantation is experimentally demonstrated in this work. This could enable SiGe p-channel field-effect transistors (pFETs) with high compres
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd20888b0b4dbccf5c8806fbc2f14ab9
https://doi.org/10.1109/ted.2021.3059256
https://doi.org/10.1109/ted.2021.3059256
Autor:
Roberto Annunziata, O. Weber, J. Jasse, Paola Zuliani, V. Caubet, Franck Arnaud, G. Samanni, Enrico Gomiero, L. Favennec, R. Berthelon, D. Ristoiu, C. Jahan, L. Clement, J. P. Reynard, R. Ranica
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 7, Pp 517-521 (2019)
Quenching-time characterization is the way to measure the speed of chalcogenide material to transform from the amorphous (RESET) state to the crystalline (SET) one after application of a proper programming pulse. It is here proposed to study the impa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::930b1b015adb15c3586cc459f3581efb
https://doi.org/10.1109/jeds.2019.2913467
https://doi.org/10.1109/jeds.2019.2913467
Autor:
Eugene Y.-J. Kong, Walter Schwarzenbach, Anne Vandooren, Bich-Yen Nguyen, Olivier Weber, Chen Sun, Aaron Thean, Christophe Maleville, Xiao Gong, Haiwen Xu, V. Barral, R. Berthelon, Franck Arnaud, Jie Liang
Publikováno v:
2020 IEEE Symposium on VLSI Technology.
For the first time, ion implant was used to partially relax the tensile strain by half in the fully-depleted (FD) strained SOI (SSOl) so that SiGe pFETs with a higher compressive strain can be realized at a fixed Ge composition. This enables the co-i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::02e01087f9ea383e2fb876f76228abe7
https://doi.org/10.1109/vlsitechnology18217.2020.9265070
https://doi.org/10.1109/vlsitechnology18217.2020.9265070
Autor:
Didier Dutartre, Sylvie Ortolland, Michel Haond, Emmanuel Josse, Francois Andrieu, R. Nicolas, Alain Claverie, Thierry Poiroux, E. Baylac, R. Berthelon
Publikováno v:
Solid-State Electronics
Solid-State Electronics, 2017, 128, pp.72-79. ⟨10.1016/j.sse.2016.10.011⟩
Solid-State Electronics, Elsevier, 2017, 128, pp.72-79. ⟨10.1016/j.sse.2016.10.011⟩
Solid-State Electronics, 2017, 128, pp.72-79. ⟨10.1016/j.sse.2016.10.011⟩
Solid-State Electronics, Elsevier, 2017, 128, pp.72-79. ⟨10.1016/j.sse.2016.10.011⟩
The introduction of strained channel is mandatory to achieve high performance in Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI) technology. Especially, compressive SiGe channel has been demonstrated to enhance hole
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2be0fe58898ee72276d44b6166cc9b83
https://doi.org/10.1016/j.sse.2016.10.011
https://doi.org/10.1016/j.sse.2016.10.011
Autor:
F. Balestra, A. Makosiej, Joris Lacord, Maud Vinet, Laurent Brunet, E. Esmanhotto, Francois Andrieu, Marco Rios, J. Cluzel, G. Cibrario, Perrine Batude, Olivier Weber, R. Berthelon, D. Lattard, D. Bosch, L. Ciampolini, Claire Fenouillet-Beranger, J.-P. Colinge, Bastien Giraud, S. Lang, Xavier Garros
Publikováno v:
2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).
For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty as well as the capability to route two additional row-wise signals on in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6339fddbd9f229a6f65ff13fd410189d
https://doi.org/10.1109/vlsi-tsa.2019.8804649
https://doi.org/10.1109/vlsi-tsa.2019.8804649
Autor:
Francois Andrieu, Joris Lacord, R. Berthelon, Laurent Brunet, A. Makosiej, Olivier Weber, C. Fenouillet-Beranger, X. Garros, G. Cibrario, D. Lattard, J.-P. Colinge, J. Cluzel, Lorenzo Ciampolini, D. Bosch, Perrine Batude, F. Balestra, Bastien Giraud
Publikováno v:
Solid-State Electronics. 168:107720
For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty, as well as the capability to route two additional row-wise signals on i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::693fb96b0d9182cfb46ea634695f9b9a
https://doi.org/10.1016/j.sse.2019.107720
https://doi.org/10.1016/j.sse.2019.107720
Publikováno v:
Extended Abstracts of the 2018 International Conference on Solid State Devices and Materials.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9c591225a5ce1c358c0b8e0f57c40662
https://doi.org/10.7567/ssdm.2018.c-3-02
https://doi.org/10.7567/ssdm.2018.c-3-02
Autor:
C. Fenouillet-Beranger, Perrine Batude, G. Cibrario, G. Tricaud, R. Boumchedda, Pierre Morin, Franck Arnaud, Laurent Brunet, O. Rozeau, Bastien Giraud, Sebastien Thuries, M. Vinet, Joris Lacord, R. Berthelon, S. Guissi, D. Fried, B. Mathieu, O. Billoint, Francois Andrieu, J.-P. Noel, A. Ayres de Sousa, E. Avelar
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
We have fabricated 3D-monolithic transistors on two tiers. We experimentally evidence the asymmetric double-gate (DG) behavior of a top-tier transistor, resulting in a better ON-state current (Ion) / OFF-state current (I off ) tradeoff than in single
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0dc4ba1dc97a9317eb210e8ddb6f1d5d
https://doi.org/10.1109/iedm.2017.8268428
https://doi.org/10.1109/iedm.2017.8268428