Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Qinghua Duan"'
Publikováno v:
ACM Great Lakes Symposium on VLSI
Modern FPGA has complex interconnect, like curve wires and two-level local muxs (global wires -> block input pins). Existing interconnect model (CB-SB) cannot describe these routing fabrics, hindering CAD exploration of modern FPGA. This paper presen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4d9ff857685618df85d83b63263c585a
https://doi.org/10.1145/3386263.3406927
https://doi.org/10.1145/3386263.3406927
Publikováno v:
FPGA
CAD exploration is important for designing FPGA interconnect topologies. It includes two steps: first, design a model with some parameters that can express as much architecture space. Second, use CAD flow to analyze the described interconnect archite
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4102846d5bba32a727b5747eb7d8b9fd
https://doi.org/10.1145/3373087.3375372
https://doi.org/10.1145/3373087.3375372
Publikováno v:
ASICON
An increasing number of high-performance computing system developed on FPGA devices need access to mass storage devices for storing data, the serial ATA protocol is widely used in the modern computer systems for transferring data between the host and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a8c864863a44f59e9d1a500919a2c93e
https://doi.org/10.1109/asicon47005.2019.8983634
https://doi.org/10.1109/asicon47005.2019.8983634
Publikováno v:
ACM Great Lakes Symposium on VLSI
As the capacity of FPGA increases, FPGA placers that adopt Simulated Annealing (SA) algorithm take more and more runtime. To solve this problem, this paper presents HCAS, a Hybrid algorithm Combining Analytical method and SA. There are three modifica
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fd18fcb5d1e88568773d5ec042488f7f
https://doi.org/10.1145/3299874.3318035
https://doi.org/10.1145/3299874.3318035
Publikováno v:
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
In this paper, we present a new hyper-graph partitioning algorithm (MKHP) for 3D-FPGA circuits. Our scheme which based on multilevel paradigm has three phases. In coarsening phase, we use hyper-edge first coarsening scheme (HFC) to obtain a coarser h
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::35aa59eb9d5284a975f3c51b590fb8be
https://doi.org/10.1109/icsict.2018.8565776
https://doi.org/10.1109/icsict.2018.8565776
Publikováno v:
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
A delay model is presented in this paper to estimate path delay during routing for GRM based FPGA. The model is linear, and factors like the structure of interconnect switch, wire length, load are analyzed to estimate the delay. In contrast to Elmore
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cbce26c782512f4abdb1b88717c4d6a0
https://doi.org/10.1109/icsict.2018.8565010
https://doi.org/10.1109/icsict.2018.8565010
Autor:
Xinxuan Tao, Qinghua Duan, Jian Wang, Meng Yang, Zhiqian Zhang, Jinmei Lai, Yuchen Yao, Jiabao Gao
Publikováno v:
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
Convolution Neural Network (CNN) has been widely used in many computer vision tasks. Due to the rapid growth of CNN, the accelerator that only supports single network could not meet the requirement of application. Based on the work of ZynqNet, which
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c8997f1c06a38ff23cb8746af5c1e1e1
https://doi.org/10.1109/icsict.2018.8565657
https://doi.org/10.1109/icsict.2018.8565657
Autor:
He Yifeng, Thomas J. Zolper, Hongwei Sun, Xingliang He, Xuejin Shen, Pinzhi Liu, Qian Wang, Qinghua Duan, Yuzhen Zhao
Publikováno v:
Friction. 3:243-255
This paper reports a series of studies on the lubricant properties, elastohydrodynamic film thickness, and coefficients of friction of several commercially available ester base stocks, i.e., diisooctyl phthalate (DIOP), diisodecyl phthalate (DIDP), d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9c3ec5ce116f0d2931f7d1c601bf998c
https://doi.org/10.1007/s40544-015-0090-6
https://doi.org/10.1007/s40544-015-0090-6
Publikováno v:
ASICON
Projects involving both software design and hardware design are usually retarded by expensive equipments, complex simulation and challenging modification. In order to retrench the designers' time and economic costs in SW/HW (Software/Hardware) co-des
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::299b38b5e412e2480fbe1fa5952f8416
https://doi.org/10.1109/asicon.2017.8252498
https://doi.org/10.1109/asicon.2017.8252498
Autor:
Qinghua Duan, Yong Zhang, Jinqiang Jiang, Kuilin Deng, Taoyi Zhang, Ping Xie, Rongben Zhang, Pengfei Fu
Publikováno v:
Polymer International; Jan2004, Vol. 53 Issue 1, p113-120, 8p