Zobrazeno 1 - 10
of 36
pro vyhledávání: '"Pushkar Ranade"'
Publikováno v:
Iranian Journal of Neurosurgery, Vol 7, Iss 2, Pp 75-84 (2021)
Background and Aim: The major concerns related to the Endoscopic Endonasal Transsphenoidal (EET) surgery for sellar and suprasellar tumors include the risks of post-operative Cerebrospinal Fluid (CSF) leak, leading to morbidity and at times mortality
Externí odkaz:
https://doaj.org/article/0bad86f3642a49c28ccc2ca7d0c5c39b
Publikováno v:
International Surgery Journal. 5:1310
Background: Acute intestinal obstruction is one of the major surgical emergencies. Intestinal obstruction is defined as partial or complete interference with forward flow of small or large intestinal contents. Intestinal obstruction of either small o
Publikováno v:
Applied Surface Science. 224:73-76
Dopant activation annealing of an elevated Ge-S/D structure formed on Si was investigated for application in advanced CMOSFET fabrication. Due to the low melting point of Ge, dopant activation was observed below 600 °C. However, the low temperature
Autor:
Leland Chang, Chenming Hu, Jeffrey Bokor, Yang-Kyu Choi, Shiying Xiong, Daewon Ha, Tsu-Jae King, Pushkar Ranade
Publikováno v:
Proceedings of the IEEE. 9:1860-1873
Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the
Publikováno v:
IEEE Transactions on Electron Devices. 49:1436-1443
This work summarizes the results of several experiments to investigate the potential applications of Silicon-Germanium alloy in the fabrication of shallow source/drain (S/D) extension Junctions for deep submicron PMOS transistors. Two approaches were
Autor:
M. Wojko, G. Krishnan, Vineet Agrawal, Mitsuaki Hori, S. Wakayama, Samuel Leshner, T. Yamada, Taiji Ema, J. Mitani, D. Zhao, T. Bakishev, Lawrence T. Clark, T. Tsuruta, S. Moriwaki, N. Kepler, Robert Rogenmoser, Pushkar Ranade, R. Roy, David A. Kidd
Publikováno v:
CICC
An SoC with ARM® Cortex™-M0 CPU cores and SRAMs is implemented in both 65nm baseline and Deeply Depleted Channel™ (DDC) technologies. DDC technology demonstrates more than 50% active and static power reduction for the CPU cores at matched 350 MH
A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits
Autor:
J. Mitani, T. Bakhishev, Taiji Ema, Y. Liu, D. Zhao, M. Duane, Yasunobu Torii, Kazushi Fujita, Y. Asada, D. Kidd, H. Ahn, Mitsuaki Hori, Thomas Hoffmann, J. Nagayama, L. Scudder, S. Pradhan, L. T. Clark, R. Rogenmoser, P. Gregory, S. Lee, D. Kanai, M. Wojko, Scott E. Thompson, Lucian Shifren, Pushkar Ranade, E. Boling
Publikováno v:
2012 International Electron Devices Meeting.
65nm Deeply Depleted Channel (DDCTM) transistors have been fabricated with a halo-free, un-doped epitaxial channel and enable reduced threshold voltage (V T ) variation, lower supply voltage (V CC ), enhanced body effect and I EFF . Digital circuits
Publikováno v:
IEEE Electron Device Letters. 23:342-344
The dependence of metal and polysilicon gate work-functions on the underlying gate dielectric in advanced MOS gate stacks is explored. We observe that the metal workfunctions on high-/spl kappa/ dielectrics differ appreciably from their values on SiO
Publikováno v:
Applied Physics Letters. 80:3706-3708
Rapid intermixing of Ge deposited onto a Si substrate during 900 °C rapid thermal annealing was analyzed using secondary ion mass spectroscopy. In undoped Ge samples, a 50 nm thick graded Si1−xGex layer was formed in 1 min, consuming 30 nm Ge and
Publikováno v:
IEEE Electron Device Letters. 23:200-202
In this letter, we present dual work function metal gate complementary metal-oxide semiconductor (CMOS) transistors with thin SiO/sub 2/ gate dielectric fabricated through the interdiffusion of nickel and titanium. The threshold voltage of the n-MOS