Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Pu-Shan Huang"'
Publikováno v:
Applied Sciences, Vol 7, Iss 7, p 739 (2017)
Measurements of the curvatures and warpages of a printed circuit board (PCB) during a thermal solder reflow process using strain gauges are proposed in this study. In the experiments, a shadow moiré is used for measuring the out-of-plane deformation
Externí odkaz:
https://doaj.org/article/b6b800c99dea4327946e64ad792c45da
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 20:442-451
The easy-to-use point-load on elastic foundation (PoEF) test, similar (or alternative) to a typical biaxial bending ball-on-ring test, is studied for determining the bending strength of thin silicon dies. The feasibility of this test method with a li
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f1de4692786d377ba0026bf2953b7df1
https://doi.org/10.1109/tdmr.2020.2987010
https://doi.org/10.1109/tdmr.2020.2987010
Publikováno v:
2015 10th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).
Fatigue characteristics of polyimide thin film strips prepared with realistic wafer-level redistribution processes were investigated experimentally. Uniaxial tensile tests were first conducted on the thin film specimens to characterize the stress-str
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c6e4edc0214a34ac51b57b1f94eb43cc
https://doi.org/10.1109/impact.2015.7365229
https://doi.org/10.1109/impact.2015.7365229
Publikováno v:
Applied Sciences, Vol 7, Iss 7, p 739 (2017)
Applied Sciences; Volume 7; Issue 7; Pages: 739
Applied Sciences; Volume 7; Issue 7; Pages: 739
Measurements of the curvatures and warpages of a printed circuit board (PCB) during a thermal solder reflow process using strain gauges are proposed in this study. In the experiments, a shadow moiré is used for measuring the out-of-plane deformation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ce230e6040fcebfc4c89f1ac8d4a35ea
https://doi.org/10.3390/app7070739
https://doi.org/10.3390/app7070739
Autor:
Pu Shan Huang, 黃溥膳
103
The 3-D integration of integrated circuit (IC) chips is to bring significant benefits to IC packaging by providing better electrical performance, lower power consumption, and smaller form factor. Currently the technology of through-silicon v
The 3-D integration of integrated circuit (IC) chips is to bring significant benefits to IC packaging by providing better electrical performance, lower power consumption, and smaller form factor. Currently the technology of through-silicon v
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/64049970167383966013
Autor:
Pu Shan Huang, 黃溥膳
97
In the application of 3-D packages or stacked die packages, most of the silicon wafers have to be ground thinner, and then the strength data of the dies cut from the wafers are needed for further assuring good design and reliability of the pa
In the application of 3-D packages or stacked die packages, most of the silicon wafers have to be ground thinner, and then the strength data of the dies cut from the wafers are needed for further assuring good design and reliability of the pa
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/01031270276000484280