Zobrazeno 1 - 10
of 57
pro vyhledávání: '"Priyank Kalla"'
Publikováno v:
2022 IEEE International Test Conference India (ITC India).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a4f6e7fc0f7c0be112c20e8d26905cba
https://doi.org/10.1109/itcindia202255192.2022.9854738
https://doi.org/10.1109/itcindia202255192.2022.9854738
Publikováno v:
VLSI-SoC
This paper addresses the rectification of faulty finite field arithmetic circuits by computing patch functions at internal nets using techniques from polynomial algebra. Contemporary approaches that utilize SAT solving and Craig interpolation are inf
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f63b20e6e4bd6387393994a8b02e98b0
https://doi.org/10.1109/vlsi-soc53125.2021.9606976
https://doi.org/10.1109/vlsi-soc53125.2021.9606976
Publikováno v:
2021 IEEE 39th International Conference on Computer Design (ICCD).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5149a7536cca8a68e8c459244f37af6f
https://doi.org/10.1109/iccd53106.2021.00039
https://doi.org/10.1109/iccd53106.2021.00039
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38:576-588
Recent developments in formal verification of arithmetic datapaths make efficient use of symbolic computer algebra algorithms. The circuit is modeled as an ideal in polynomial rings, and Grobner basis (GB) reductions are performed over these polynomi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::05bb768471b9537da29cf565542994cd
https://doi.org/10.1109/tcad.2018.2818726
https://doi.org/10.1109/tcad.2018.2818726
Publikováno v:
ISQED
Deciding whether a faulty circuit can be rectified at a given set of nets to match its intended specification constitutes a critical problem in post-verification debugging and rectification. Contemporary approaches which utilize Boolean SAT and Craig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::182e10de19a3d0a55eed13c9efbbeec1
https://doi.org/10.1109/isqed51717.2021.9424286
https://doi.org/10.1109/isqed51717.2021.9424286
Publikováno v:
ETS
When formal verification identifies the presence of a bug in a design, it is required to rectify the circuit at some net(s). Modern approaches formulate the rectification test as an unsatisfiability proof, and then use Craig interpolants (CI) in prop
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::735506f50695a1b092a359d64aa15383
https://doi.org/10.1109/ets.2019.8791541
https://doi.org/10.1109/ets.2019.8791541
Publikováno v:
VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms ISBN: 9783030234249
VLSI-SoC (Selected Papers)
VLSI-SoC (Selected Papers)
When formal verification of arithmetic circuits identifies the presence of a bug in the design, the task of rectification needs to be performed to correct the function implemented by the circuit so that it matches the given specification. In our rece
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b05ceee5d22fdae6b59aa9bf42036fbd
https://doi.org/10.1007/978-3-030-23425-6_5
https://doi.org/10.1007/978-3-030-23425-6_5
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35:1206-1218
This paper introduces a technique to derive a word-level abstraction of the function implemented by a combinational logic circuit. The abstraction provides a canonical representation of the function as a polynomial ${Z} {= {\mathcal {F}}(A)}$ over th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::35e2e1315ff5514dc35ff71449913478
https://doi.org/10.1109/tcad.2015.2501301
https://doi.org/10.1109/tcad.2015.2501301
Publikováno v:
FMCAD
Formal verification of arithmetic circuits checks whether or not a gate-level circuit correctly implements a given specification model. In cases where this equivalence check fails – the presence of a bug is detected – it is required to: i) debug
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f7b95cd83af6f9139b0528288e60d5d
https://doi.org/10.23919/fmcad.2018.8603018
https://doi.org/10.23919/fmcad.2018.8603018
Publikováno v:
VLSI-SoC
When formal verification of arithmetic circuits identifies the presence of a bug in the design, the task of rectification needs to be performed to correct the function implemented by the circuit so that it matches the given specification. This paper
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::22b70093ddb0dd4927ddaada12dd8dd7
https://doi.org/10.1109/vlsi-soc.2018.8644853
https://doi.org/10.1109/vlsi-soc.2018.8644853