Zobrazeno 1 - 10
of 643
pro vyhledávání: '"Precise exceptions"'
Publikováno v:
2022 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::36b55c4d8242fd43af4e0fcbb6ef4493
https://doi.org/10.1109/ispass55109.2022.00031
https://doi.org/10.1109/ispass55109.2022.00031
Conference
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Kniha
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Akademický článek
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Autor:
Michael K. Gschwind, Erik R. Altman
Publikováno v:
ACM SIGARCH Computer Architecture News. 29:66-74
Maintaining precise exceptions is an important aspect of achieving full compatibility with a legacy architecture. While asynchronous exceptions can be deferred to an appropriate boundary in the code, synchronous exceptions must be taken when they occ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3e7c3fab8d853941760706a75b64c169
https://doi.org/10.1145/373574.373592
https://doi.org/10.1145/373574.373592
Autor:
Hyesoon Kim
Publikováno v:
MSPC
Supporting precise exceptions has been one of the essential components of designing modern out-of-order processors. It allows handling exception routines, including virtual memory support and also supports debugging features. However, GPGPU, one of t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::67e4c0f53bd96f50e1bd1d2f6a6e8325
https://doi.org/10.1145/2247684.2247698
https://doi.org/10.1145/2247684.2247698
Autor:
Nasr Ullah, Matt Holle
Publikováno v:
ACM SIGARCH Computer Architecture News. 21:15-25
This paper describes the precise exception model of the MC88110 symmetric superscalar microprocessor. The MC88110 is a superscalar, pipelined processor that contains multiple exection units and allows out-of order execution of instructions. The MC881
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::199a2b25519ec69afecf95bd60f4839d
https://doi.org/10.1145/152479.152482
https://doi.org/10.1145/152479.152482
Publikováno v:
ARVLSI
The presence of precise exceptions in a processor leads to complications in its design. Some recent processor architectures have sacrificed this requirement for performance reasons at the cost of software complexity. We present an implementation stra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::445c94c03796e41ef8c369c7dad65cdf
https://doi.org/10.1109/arvlsi.2001.915547
https://doi.org/10.1109/arvlsi.2001.915547
Autor:
R.K. Shyamasundar, K. Kalyanasundaram
Publikováno v:
MEMOCODE
Verification of pipelined processors is a complex and challenging issue. In this paper, we develop a methodology based on translation validation for the verification of pipelined processors that support precise exceptions and out-of-order executions.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::32be70eb4c41bff19f80ae5dc805d0c8
https://doi.org/10.1109/memcod.2004.1459832
https://doi.org/10.1109/memcod.2004.1459832
Publikováno v:
Languages and Compilers for Parallel Computing ISBN: 9783540211990
LCPC
LCPC
Partial redundancy elimination can reduce the number of loads corresponding to field and array accesses in Java programs. The reuse of values loaded from memory at subsequent occurrences of load expressions must be done with care: Precise exceptions
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8b7f273fb25f3c94b87436ec194a2793
https://doi.org/10.1007/978-3-540-24644-2_25
https://doi.org/10.1007/978-3-540-24644-2_25
