A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAMs

Autor: Behzad Zeinali, Jens Kargaard Madsen, Farshad Moradi, Praveen Raghavan

Publikováno v: Zeinali, B, Madsen, J K, Raghavan, P & Moradi, F 2019, ' A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAMs ', IEEE Transactions on Emerging Topics in Computing, vol. 7, no. 2, 7744549, pp. 294-300 . https://doi.org/10.1109/TETC.2016.2629090

A combination of semiconductor integrated circuits (IC) and a dense array of scaled magnetic tunnel junctions (MTJ) makes promising Spin-Transfer Torque Random Access Memory (STT-RAM). This emerging memory minimizes the leakage power consumption and

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ba469b270edb9c97d8397df6a288138f
https://doi.org/10.1109/tetc.2016.2629090

Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI

Autor: P. Schuddinck, Max M. Shulaker, Romain Ritzenthaler, Alessio Spessot, Dimitrios Rodopoulos, Chi-Shuen Lee, Praveen Raghavan, Aaron Thean, Peter Debacker, Luca Mattii, Francky Catthoor, Syed Muhammed Yasser Sherazi, Marie Garcia Bardon, D. Yakimets, Rogier Baert, Gage Hills, Subhasish Mitra, H.-S. Philip Wong, Doyoung Jang, Gerben Doornbos, Iuliana Radu

Publikováno v: IEEE Transactions on Nanotechnology. 17:1259-1269

© 2018 IEEE. Carbon Nanotube Field-Effect Transistors (CNFETs) are highly promising to improve the energy efficiency of digital logic circuits. Here, we quantify the Very-Large-Scale Integrated (VLSI) circuit-level energy efficiency of CNFETs versus

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a0c3d32c29c32be8a49eb7552ab3243f
https://doi.org/10.1109/tnano.2018.2871841

MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts

Autor: Lutong Wang, Peter Debacker, Kwangsoo Han, Praveen Raghavan, Andrew B. Kahng, Hyein Lee

Publikováno v: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36:1075-1088

Self-aligned multiple patterning, due to its low overlay error, has emerged as the leading option for 1-D gridded back-end-of-line (BEOL) in sub-14-nm nodes. To form actual routing patterns from a uniform “sea of wires,” cut masks are needed for

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::662e23b3169df1c84d617413b8dd1785
https://doi.org/10.1109/tcad.2017.2685594

Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier

Autor: Praveen Raghavan, Innocent Agbo, Said Hamdioui, Pieter Weckx, Francky Catthoor, Halil Kukner, Mottaqiallah Taouil, Daniel Kraak

Publikováno v: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:1444-1454

The CMOS technology scaling faced over the past recent decades severe variability and reliability challenges. One of the major reliability challenges is bias temperature instability (BTI). This paper analyzes the impact of BTI on the sensing delay of

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a43ef70e3d7e8222d9d497acfa497145
https://doi.org/10.1109/tvlsi.2016.2643618

Sense amplifier offset voltage analysis for both time-zero and time-dependent variability

Autor: Innocent Agbo, Wim Dehaene, Daniel Kraak, Francky Catthoor, Said Hamdioui, Mottaqiallah Taouil, Stefan Cosemans, Praveen Raghavan, Pieter Weckx

© 2019 This paper presents an accurate technique to extensively analyze the impact of time-zero (i.e., global and local variation) and time-dependent (i.e., voltage, temperature, workload, and aging) variation on the offset voltage specification of

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6292f1684d4c01620519ca4977c264fc
https://lirias.kuleuven.be/handle/123456789/644537