Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Praveen Kumar Venkatachala"'
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 68:2327-2331
This brief presents a high-resolution ADC which makes use of the pseudo-pseudo-differential noise filtering technique in an oversampling ADC architecture with ring amplifier based integrators. The pseudo-pseudo-differential noise filtering technique
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::518674476413492d6f459a93b6c20104
https://doi.org/10.1109/tcsii.2021.3060011
https://doi.org/10.1109/tcsii.2021.3060011
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 67:600-610
A highly reconfigurable charge-domain switched- $g_{\mathrm {m}}$ -C biquad band-pass filter (BPF) topology that utilizes an interleaved semi-passive charge-sharing technique is proposed. It uses only switches, capacitors, linearity-enhanced $g_{\mat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0457d7bdf2be365893bf742e88b7f3df
https://doi.org/10.1109/tcsi.2019.2949018
https://doi.org/10.1109/tcsi.2019.2949018
Autor:
Koichi Hamashita, Kazuki Sobue, Praveen Kumar Venkatachala, Ahmed ElShater, Spencer Leuenberger, Jason Muhlestein, Un-Ku Moon, Calvin Yoji Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:3410-3420
Low-noise ring amplifiers required for high-precision analog–digital converters (ADCs) greater than 16 b remain unexplored. This article demonstrates a two-step successive approximation (SAR) ADC achieving 91-dB signal-to-noise-and-distortion-ratio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8065b282162dfbba25d1b1bb304a4352
https://doi.org/10.1109/jssc.2019.2943935
https://doi.org/10.1109/jssc.2019.2943935
Autor:
Ajmal Vadakkan Kayyil, David J. Allstot, Narayana Bhagirath Thota, Praveen Kumar Venkatachala, Chaiyanut Aueamnuay
Publikováno v:
ISCAS
The g m /I D -based design of analog integrated circuits introduced by Silveira, et al. in 1996 [1] employs an empirical transistor sizing methodology using SPICE-generated lookup tables that enables good agreement between simulations and specificati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6ade01c7c217b08bd031f82f278e494f
https://doi.org/10.1109/iscas45731.2020.9180575
https://doi.org/10.1109/iscas45731.2020.9180575
Autor:
Un-Ku Moon, Calvin Yoji Lee, Spencer Leuenberger, Qadeer A. Khan, Praveen Kumar Venkatachala, Bohui Xiao, Yang Xu, Ahmed ElShater
Publikováno v:
A-SSCC
This paper presents a capacitor-less low dropout (LDO) regulator that requires no frequency compensation, with the use of an adaptive-deadzone ring amplifier. Due to the dynamic behavior of the ring amplifier depending on the input voltage, the propo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0a69425f43e5bb1bca1e3de46ca824e7
https://doi.org/10.1109/a-sscc47793.2019.9056970
https://doi.org/10.1109/a-sscc47793.2019.9056970
Publikováno v:
ISCAS
A digital subsampling ADC-PLL is simulated using Verilog-A models with ring-amplifier designed in a 65nm CMOS process. The ADC-PLL utilizes a ring-amplifier to relax the design requirements of the ADC. The ring-amplifier provides high open loop gain
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ada0fdade5b487dfb1155a4ad7b4a676
https://doi.org/10.1109/iscas.2019.8702142
https://doi.org/10.1109/iscas.2019.8702142
Publikováno v:
ISCAS
In this paper, a modified assisted opamp technique is proposed for power saving. The original assisted opamp technique adds assistance circuitry to an integrator that results in significant linearity enhancement. The original method utilizes an analo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3df0e3b3c2f574627387e6214987b1ad
https://doi.org/10.1109/iscas.2019.8702717
https://doi.org/10.1109/iscas.2019.8702717
Publikováno v:
ISCAS
This paper presents a method of biasing high gain ring amplifiers with cascoded output stages while retaining the high slew capability of the ring amplifier. The proposed method biases all devices in the output stage using voltages from the previous
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8f11bbf427abc7b729b2d56178877afe
https://doi.org/10.1109/iscas.2019.8702710
https://doi.org/10.1109/iscas.2019.8702710
Autor:
Ahmed ElShater, Jason Muhlestein, Spencer Leuenberger, Praveen Kumar Venkatachala, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon, Calvin Yoji Lee
Publikováno v:
ISSCC
The two-step SAR architecture has been a popular choice for power-efficient ADCs used in applications such as medical imaging. The simple and scalable architecture of the SAR ADC enables efficient multi-bit conversion per stage [1, 2] however, the ma
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bc6f8e4f02e3871b24e6b2c3523aa784
https://doi.org/10.1109/isscc.2019.8662400
https://doi.org/10.1109/isscc.2019.8662400
Autor:
Ahmed ElShater, Spencer Leuenberger, Un-Ku Moon, Calvin Yoji Lee, Michael Oatman, Bohui Xiao, Praveen Kumar Venkatachala
Publikováno v:
ISCAS
The design of a successive approximation analog-to-digital converter with dynamic redundancy algorithm is proposed. The dynamic redundancy algorithm reduces comparator pre-amplifier activity by completing conversions at an accelerated speed and power
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::732b12065ce737dad62cbd972c945061
https://doi.org/10.1109/iscas.2018.8351126
https://doi.org/10.1109/iscas.2018.8351126