Zobrazeno 1 - 10
of 30
pro vyhledávání: '"Pranita Kulkarni"'
Autor:
D. K. Sadana, S. W. Bedell, K. Fogel, Nicolas Daval, Ali Khakifirooz, Anthony G. Domenicucci, Pranita Kulkarni
Publikováno v:
Microelectronic Engineering. 88:324-330
A thin body (fully depleted) strained SGOI device structure (FDSGOI), and a strained SiGe channel layer on SOI, were fabricated using scaled [email protected] gate dielectrics and metal gate technology. The uniaxial strain effect and corresponding dr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::11b1584d228d5cf305424b4280e5d572
https://doi.org/10.1016/j.mee.2010.08.002
https://doi.org/10.1016/j.mee.2010.08.002
Autor:
Shom Ponoth, Arvind Kumar, J. Kuss, Pranita Kulkarni, Frederic Boeuf, Ali Khakifirooz, Balasubramanian S. Haran, Effendi Leobandung, Kangguo Cheng, Qing Liu, Mukesh Khare, Maud Vinet, Scott Luning, Masami Hane, T. Yamamoto, Nicolas Loubet, Prasanna Khare, Walter Kleemeier, Terence B. Hook, Frederic Monsieur, Mariko Takayanagi, Thomas Skotnicki, Stephane Monfray, Huiming Bu, Ron Sampson, Kazunari Ishimaru, Sanjay Mehta, Jin Cai, Bruce B. Doris, Atsushi Yagishita
Publikováno v:
ECS Transactions. 34:37-42
We report fully-depleted UTBB devices with a gate length (LG) of 25nm and BOX thickness (TBOX) at 25nm, fabricated with a 22nm technology ground rule, featuring conventional gate first high-K/metal and raised source/drain (RSD) process. Competitive d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::148eaf103c2cef33d9dfa1a0b2d0786f
https://doi.org/10.1149/1.3567556
https://doi.org/10.1149/1.3567556
Opportunities and Challenges of FinFET as a Device Structure Candidate for 14nm Node CMOS Technology
Autor:
Vamsi Paruchuri, Andres Bryant, Bruce B. Doris, Tenko Yamashita, Hiroshi Sunamura, Effendi Leobandung, Hemanth Jagannathan, Junli Wang, Atsuro Inada, Theodorus E. Standaert, Pranita Kulkarni, Robert J. Miller, Johnathan E. Faltermeier, Kingsuk Maitra, Huiming Bu, Veeraraghavan S. Basker, James A. O’Neill, Sivananda K. Kanakasabapathy, Chung-Hsun Lin, T. Yamamoto, Chun-Chen Yeh, Jin Cho, Mukesh Khare
Publikováno v:
ECS Transactions. 34:81-86
FinFET is a promising device candidate for 14nm node CMOS technology. We have developed FinFET device showing superior short channel control at 25nm gate length. This FinFET device featuring gate first high-k/metal gate and merged Epi source/drain pr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3e339ce32c67c3b83707e7e70c7cdb6b
https://doi.org/10.1149/1.3567563
https://doi.org/10.1149/1.3567563
Autor:
Stefan Schmitz, Ghavam G. Shahidi, Soon-Cheon Seo, Steven J. Holmes, Alexander Reznicek, Devendra K. Sadana, James J. Demarest, Pranita Kulkarni, Ali Khakifirooz, Kangguo Cheng, Thomas N. Adam, Lisa F. Edge, Yu Zhu, R. Johnson, Bruce B. Doris, Huiming Bu, Sivananda K. Kanakasabapathy, Hong He
Publikováno v:
ECS Transactions. 27:951-957
Fully depleted SOI (FDSOI) is a viable option for continued CMOS scaling. In this paper, we overview key challenges for designing and manufacturing extremely thin SOI (ETSOI) devices and provide solutions to each challenge. We demonstrate successful
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::505c5818f992b7abe511c40162398b04
https://doi.org/10.1149/1.3360735
https://doi.org/10.1149/1.3360735
Autor:
Ghavam G. Shahidi, Ali Khakifirooz, Bruce B. Doris, Devendra K. Sadana, Stephen W. Bedell, Pranita Kulkarni, Kangguo Cheng
Publikováno v:
ECS Transactions. 33:489-499
Limitations of conventional strain engineering methods for fully-depleted SOI structure are reviewed and methods to extend these approaches to future FDSOI devices are discussed. The application of global strain engineering combined with biaxial to u
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5e51181dd86292948c66efff558daa0e
https://doi.org/10.1149/1.3487579
https://doi.org/10.1149/1.3487579
Autor:
Pranita Kulkarni, Ghavam G. Shahidi, Jin Cai, Isaac Lauer, K.K. Chan, Zhibin Ren, Young-Hee Kim, Ramachandran Muralidhar, P. Oldiges, Dae-Gyu Park
Publikováno v:
IEEE Electron Device Letters. 33:776-778
The short-channel effects (SCEs) of planar bulk and fully depleted finFET devices have been compared using the same junction overlap and lateral gradient, and it is shown that, for finFET devices, a significant component of electrostatic control aris
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::45cb4d834c44acc9b5170d6c211d98ce
https://doi.org/10.1109/led.2012.2192411
https://doi.org/10.1109/led.2012.2192411
Autor:
Bruce B. Doris, Juntao Li, Ali Khakifirooz, Thomas N. Adam, Hong He, Qing Liu, Alexander Reznicek, Shom Ponoth, J. Kuss, Ghavam G. Shahidi, Kangguo Cheng, Nicolas Loubet, Pranita Kulkarni, Raghavasimhan Sreenivasan
Publikováno v:
IEEE Electron Device Letters. 33:149-151
We report high-performance extremely thin SOI MOSFETs fabricated with a channel thickness down to 3.5 nm, sub-20-nm gate length, and contacted gate pitch of 100 nm. At an effective channel length of 18 nm, a drain-induced barrier lowering of 100 mV i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::048fe1f38b9effe4be97f54facf80002
https://doi.org/10.1109/led.2011.2174411
https://doi.org/10.1109/led.2011.2174411
Autor:
R. J. Miller, J. Faltermeier, Pranita Kulkarni, Bruce B. Doris, Kingsuk Maitra, D. McHerron, N R Klymko, E Leobundung, H. Adhikari, Huiming Bu, Chun-Chen Yeh, Katherine L. Saenger, Vamsi Paruchuri, J. O'Neil, Veeraraghavan S. Basker, Ali Khakifirooz, Theodorus E. Standaert, Hemanth Jagannathan
Publikováno v:
IEEE Electron Device Letters. 32:713-715
Strained-silicon-on-insulator (SSOI) undoped-body high-κ /metal-gate n-channel fin-shaped field-effect transistors (nFinFETs) at scaled gate lengths and pitches (i.e.,LGATE ~ 25 nm and a contacted gate pitch of 130 nm) were fabricated using a gate-f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1a1ed78e22846ada1bac7635a99cdc8e
https://doi.org/10.1109/led.2011.2126556
https://doi.org/10.1109/led.2011.2126556
Autor:
Anne Kimball, Ghavam G. Shahidi, Thomas N. Adam, Ali Khakifirooz, Huiming Bu, Bruce B. Doris, Pranita Kulkarni, Kangguo Cheng, Lisa F. Edge, Alexander Reznicek, Jin Cai
Publikováno v:
IEEE Electron Device Letters. 32:267-269
We report partially depleted silicon-on-insulator p-channel field-effect transistors fabricated with a 32-nm technology ground rule and featuring SiGe raised source/drain, SiGe channel, and implant-free extension formation process. A respectable driv
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4fcdc3131405d06c53fc93811b46c2f9
https://doi.org/10.1109/led.2010.2099639
https://doi.org/10.1109/led.2010.2099639
Autor:
Andreas Kerber, Frank Yeh, Robert J. Miller, Chung-Hsun Lin, Huiming Bu, Veeraraghavan S. Basker, Kingsuk Maitra, Pranita Kulkarni, Sujata Paul, Hemanth Jagannathan
Publikováno v:
IEEE Electron Device Letters. 31:650-652
A methodology based on the transistor body effect is used to monitor inversion oxide thicknesses (Tinv's) in high-κ/metal-gate undoped ultrathin-body short-channel SOI FINFETs. The extracted Tinv's are benchmarked to independent capacitance-voltage
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::482c063490da6bf066a387154553aee6
https://doi.org/10.1109/led.2010.2049634
https://doi.org/10.1109/led.2010.2049634