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Autor:
Joo Hyun Park, Deborah Ryan, Haizhou Yin, Pouya Rezaeifakhr, Shobhit Malik, Eric Chiu, Panneerselvam Venkatachalam, Kiruthika Murali, Praneetha Poluju, Shenghua Song, Sriram Madhavan, Monisa Ramesh Babu, Qian Xie
Publikováno v:
Design-Process-Technology Co-optimization for Manufacturability XIV.
Semiconductor foundries typically analyze design layouts for criticality as a precursor to manufacturing flows. Risk assessment is performed on incoming layouts to identify and react to critical patterns at an early stage of the manufacturing cycle,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::79f9de1e6db1263bdcc99d042c7302e5
https://doi.org/10.1117/12.2551939
https://doi.org/10.1117/12.2551939
