Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Pranav Kalavade"'
Autor:
Ali Khakifirooz, Eduardo Anaya, Sriram Balasubrahrmanyam, Geoff Bennett, Daniel Castro, John Egler, Kuangchan Fan, Rifat Ferdous, Kartik Ganapathi, Omar Guzman, Chang Wan Ha, Rezaul Haque, Vinaya Harish, Majid Jalalifar, Owen W. Jungroth, Sung-Taeg Kang, Golnaz Karbasian, Jee-Yeon Kim, Siyue Li, Aliasgar S. Madraswala, Srivijay Maddukuri, Amr Mohammed, Shanmathi Mookiah, Shashi Nagabhushan, Binh Ngo, Deep Patel, Sai Kumar Poosarla, Naveen V. Prabhu, Carlos Quiroga, Shantanu Rajwade, Ahsanur Rahman, Jalpa Shah, Rohit S. Shenoy, Ebenezer Tachie Menson, Archana Tankasala, Sandeep Krishna Thirumala, Sagar Upadhyay, Krishnasree Upadhyayula, Ashley Velasco, Nanda Kishore Babu Vemula, Bhaskar Venkataramaiah, Jiantao Zhou, Bharat M. Pathak, Pranav Kalavade
Publikováno v:
2023 IEEE International Solid- State Circuits Conference (ISSCC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::177753a2ce8bb9f42c2ea9a8a3d32f41
https://doi.org/10.1109/isscc42615.2023.10067616
https://doi.org/10.1109/isscc42615.2023.10067616
Autor:
Rezaul Haque, Aliasgar S. Madraswala, Cindy Sun, Bharat M. Pathak, Jacqueline Snyder, Kristopher H. Gaewsky, Ali Khakifirooz, Binh Ngo, Chang Wan Ha, Prabhu Naveen Vittal, Karthikeyan Ramamurthi, Fastow Richard, Shantanu R. Rajwade, Owen W. Jungroth, Deepak Thimmegowda, Pranav Kalavade, Rohit S. Shenoy, Steven Law, Sriram Balasubrahmanyam
Publikováno v:
ISSCC
Continued improvement in the 3D NAND bit density is essential to satisfy the exponentially growing demand for data storage. The transition from 3b/cell (TLC) to 4b/cell (QLC) is a significant step towards delivering higher bit density. The increased
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eb44bd4a0a1dc88696b6b21df77445d2
https://doi.org/10.1109/isscc42613.2021.9365777
https://doi.org/10.1109/isscc42613.2021.9365777
Autor:
Pranav Kalavade
Publikováno v:
2020 IEEE International Memory Workshop (IMW).
This paper describes 4 bits/cell (QLC) 3D NAND based on 96 layer Floating Gate (FG) cell and CMOS under Array (CuA), achieving high areal density, performance, and reliability. More than 10million QLC FG 3D NAND SSDs have been shipped for both Client
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::459a385b6c89abd2bb8cd0d5caa68b3f
https://doi.org/10.1109/imw48823.2020.9108135
https://doi.org/10.1109/imw48823.2020.9108135
Autor:
Krishna K. Parat, Yijie Zhao, Toru Tanzawa, Pranav Kalavade, Haitao Liu, Akira Goda, A. Torsi
Publikováno v:
IEEE Transactions on Electron Devices. 58:11-16
We have developed a program-disturb model to characterize the channel potential of the program-inhibited string during NAND flash cell programming. This model includes cell-to-cell capacitances from 3-D technology computer-aided design simulation and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6758f8f01a97372d7e1b2d847fb06c58
https://doi.org/10.1109/ted.2010.2087338
https://doi.org/10.1109/ted.2010.2087338
Publikováno v:
IEEE Transactions on Electron Devices. 55:632-639
A sub-45-nm body thickness, vertical-channel, double-gate MOSFET (VDFET) is fabricated on a bulk silicon substrate. The process, in principle, is scalable down to sub-5-nm body thicknesses. It is realized that using very coarse lithography (~1 mum re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::56bf8fbcc79acd2ffeaf504ba30a97b4
https://doi.org/10.1109/ted.2007.913003
https://doi.org/10.1109/ted.2007.913003
Publikováno v:
ECS Transactions. 3:403-414
Geometry dependent thermal oxidation rates of silicon/polysilicon on concave and convex surfaces are complex and need a better understanding. The complexity is a result of several competing effects, namely, volume expansion stress, area effects, stre
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e866afe5b6e1299ea28ac9ceb1f592e7
https://doi.org/10.1149/1.2356300
https://doi.org/10.1149/1.2356300
Publikováno v:
IEEE Transactions On Nanotechnology. 5:554-563
We demonstrate vertical capacitors using a novel spacer process capable of fin thickness down to 5 nm. We also integrate this process compatibly with planar devices on the same die using minimal additional mask steps. Various implant conditions, orde
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b41f86eb439e072585e6e7e00d5859a5
https://doi.org/10.1109/tnano.2006.880881
https://doi.org/10.1109/tnano.2006.880881
Publikováno v:
IEEE Electron Device Letters. 32:1185-1187
In 25-nm NAND Flash memory, source-drain implantation conditions significantly affect random telegraph signal (RTS). In this extremely short gate length regime, RTS is proportional to the effective gate length (Leff) which exhibits an “inverse scal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::226d98be83671c296359aa479ad36e2a
https://doi.org/10.1109/led.2011.2159573
https://doi.org/10.1109/led.2011.2159573
Publikováno v:
2007 65th Annual Device Research Conference.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::12e2638dce5d86e6002173baced98383
https://doi.org/10.1109/drc.2007.4373704
https://doi.org/10.1109/drc.2007.4373704
Autor:
Pranav Kalavade, Krishna C. Saraswat
Publikováno v:
2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).
High performance near-single grain poly-Si lateral gate-all-around (GAA) MOS transistors have been demonstrated. A high I/sub ON//I/sub OFF/ ratio of 10/sup 8/ and nearly ideal subthreshold slope of 67 mV/dec were achieved. These devices were fabrica
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::609dc71bcfe7b8106520c3cee9d41c52
https://doi.org/10.1109/soic.2001.958010
https://doi.org/10.1109/soic.2001.958010