Výsledky vyhledávání - "Pramod Kolar"

Sub-550mV SRAM Design in 22nm FinFET Low Power (22FFL) Technology with Self-Induced Collapse Write Assist

Autor: Satyanand Nalam, Xiaofei Wang, Daeyeon Kim, Ayush Shrivastava, Zheng Guo, Pramod Kolar, Jinal Shah, Eric Karl, Jami Wiedemer, Gwanghyeon Baek

Publikováno v: 2018 IEEE Symposium on VLSI Technology.

Exceptionally low minimum operating voltage (V MIN ) SRAM arrays have been demonstrated on 22nm FinFET low power technology (22FFL) [1]. By optimizing an undoped SRAM transistor and applying industry standard write assist techniques, 16Mb array of 0.

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b26249d2c9ba3c0113a6f1c42f6b6db8
https://doi.org/10.1109/vlsit.2018.8510704

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A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation

Autor: Uddalak Bhattacharya, Fatih Hamzaoglu, Yong-Gee Ng, Yih Wang, Pramod Kolar, Kevin Zhang, Eric Karl, Hyunwoo Nho

Publikováno v: ISSCC

SRAM scaling faces increasing challenges in meeting power, performance, and density requirements as Moore's law continues to drive CMOS technology scaling. Due to process variation, SRAM bitcell design margin continues to shrink in scaled technologie

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f02a4ae77b544c9635a54e93700562a0
https://doi.org/10.1109/jssc.2010.2084490

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Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design

Autor: Yong-Gee Ng, Kevin Zhang, Yih Wang, Pramod Kolar, Liqiong Wei, Fatih Hamzaoglu, Uddalak Bhattacharya

Publikováno v: IEEE Design & Test of Computers. 28:22-31

Six-transistor SRAM cells have served as the workhorse embedded memory for several decades. However, with aggressive technology scaling, designers find it increasingly difficult to guarantee robust operation at low voltages because of the worsening p

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::4b465a52923303dda736ad025dac6e25
https://doi.org/10.1109/mdt.2011.5

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A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management

Autor: Uddalak Bhattacharya, Liqiong Wei, Mark T. Bohr, Yih Wang, Pramod Kolar, Yong-Gee Ng, Fatih Hamzaoglu, Ying Zhang, Kevin Zhang

Publikováno v: IEEE Journal of Solid-State Circuits. 45:103-110

This paper introduces a high-performance voltage-scalable SRAM design in a 32 nm strain-enhanced high-k + metal-gate logic CMOS technology. The 291 Mb SRAM design features a 0.171 ?m2 six-transistor bitcell that supports a broad range of operating vo

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::86b8094dc3e1e2e03dbb21284ce807b7
https://doi.org/10.1109/jssc.2009.2034082

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A 1.1 GHz 12 $\mu$A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

Autor: J. Lin, Sarvesh H. Kulkarni, Hafez Walid M, Yih Wang, F. Hamzaoglu, Uddalak Bhattacharya, M. Bohr, T. Coan, Chia-Hong Jan, Kevin Zhang, Pramod Kolar, Ian R. Post, Yong-Gee Ng, Liqiong Wei, Ying Zhang, Zhanping Chen, Hong Jo Ahn

Publikováno v: IEEE Journal of Solid-State Circuits. 43:172-179

A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications. The 65 nm strained silicon technology improves transistor performance/leakage tradeoff, which is essential to achieve fast SRAM

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1cf28bad0748ee9b4211a56c8dbd8be1
https://doi.org/10.1109/jssc.2007.907996

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A methodology for yield-specific leakage estimation in memory

Autor: Pramod Kolar, Subho Chatterjee, Gunjan H. Pandya, Jae Y Ko, Wei Jian Chan

Publikováno v: CICC

A simulation based pre-silicon leakage estimation methodology for SRAM is proposed. The methodology is easily extended to different voltage and temperature corners and it enables determination of leakage yield. It comprehends the impact of die to die

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::45b178d7aa27456c67d27abd982a4303
https://doi.org/10.1109/cicc.2014.6946133

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A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management

Autor: Liqiong Wei, Yong-Gee Ng, Pramod Kolar, Yuegang Zhang, Fatih Hamzaoglu, Uddalak Bhattacharya, M. Bohr, Yih Wang, Kevin Zhang

Publikováno v: ISSCC

CMOS technology has followed Moore's law into the nanoscale regime where SRAM scaling is facing increasing challenges in gaining performance at reduced leakage power for future product applications. Despite the advances in process technologies and th

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f934c533ba31b3926cd0881ac91e9945
https://doi.org/10.1109/isscc.2009.4977505

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Erratic fluctuations of SRAM cache Vmin at the 90nm process technology node

Publikováno v: Scopus-Elsevier

Erratic bit phenomena have been reported in advanced flash memories, and have been attributed to trapping/detrapping effects that modify the threshold voltage. This paper describes for the first time the observance of erratic behavior in SRAM Vmin, d

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0c98cc931a027fc044917ca28e022450
http://www.scopus.com/inward/record.url?eid=2-s2.0-33846061871&partnerID=MN8TOARS

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