Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Pradeep Kumar Biswal"'
Autor:
Pradeep Kumar Biswal
Publikováno v:
Journal of Electronic Testing.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::db970863c76fd36d398a8e744d3737fd
https://doi.org/10.1007/s10836-023-06066-7
https://doi.org/10.1007/s10836-023-06066-7
Autor:
Pradeep Kumar Biswal
Publikováno v:
2022 IEEE Region 10 Symposium (TENSYMP).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::61c1ae7253bb7c40b49c36775a9e6066
https://doi.org/10.1109/tensymp54529.2022.9864357
https://doi.org/10.1109/tensymp54529.2022.9864357
Autor:
Santosh Biswas, Pradeep Kumar Biswal
Publikováno v:
Journal of Electronic Testing. 35:715-727
The fast growing in complexity of digital VLSI circuits with the advance of deep sub-micron scaling causes occurrence of faults during normal operation of the circuits. These faults cannot be detected by off-line test or Built-In-Self-Test (BIST) tec
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d1ecfe3c6fc6dce5f9f0c01043a9667
https://doi.org/10.1007/s10836-019-05828-6
https://doi.org/10.1007/s10836-019-05828-6
Autor:
Pradeep Kumar Biswal, Santosh Biswas
Publikováno v:
Microelectronics Journal. 67:88-100
Nowadays On-Line Testing (OLT) has became one the essential technique to detect faults in digital VLSI circuits which occur during their normal operation. However, most of the works on OLT reported in the literature are at the gate level and these te
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e93352099c662c8fbb3b257d9e9a6a96
https://doi.org/10.1016/j.mejo.2017.08.002
https://doi.org/10.1016/j.mejo.2017.08.002
Publikováno v:
Engineering Science and Technology, an International Journal, Vol 19, Iss 3, Pp 1473-1487 (2016)
In the present era of complex systems like avionics, industrial processes, electronic circuits, etc., on-the-fly or on-line fault detection is becoming necessary to provide uninterrupted services. Measurement limitation based fault detection schemes
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7a84aeabed39b66ad9608aaa0254040c
https://doi.org/10.1016/j.jestch.2016.04.005
https://doi.org/10.1016/j.jestch.2016.04.005
Autor:
Pradeep Kumar Biswal, Santosh Biswas
Publikováno v:
VLSI Design
The rapid increase in complexity of digital VLSI circuits with the advent of Deep Sub-Micron (DSM) technology causes development of faults during their normal operation. Some non-modeled faults may not always be detectable by off-line test or Built-I
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cc303baaaab540d7e6620d05a68cf88b
https://doi.org/10.1109/vlsid.2019.00035
https://doi.org/10.1109/vlsid.2019.00035
Autor:
Pradeep Kumar Biswal, Santosh Biswas
Publikováno v:
Microelectronics Journal. 46:598-616
Classical manufacturing test verifies that a circuit is fault free during fabrication, however, cannot detect any fault that occurs after deployment or during operation. As complexity of integration rises, frequency of such failures is increasing for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cc66d76154d6b4a663595a9398467d66
https://doi.org/10.1016/j.mejo.2015.04.005
https://doi.org/10.1016/j.mejo.2015.04.005
Autor:
Pradeep Kumar Biswal, Santosh Biswas
Publikováno v:
Systems Science & Control Engineering. 3:307-319
The discrete event system (DES) has been used for failure detection and diagnosis (FDD) of a wide range of systems. The major reason for resorting to the DES framework is the simplicity in modelling and the low complexity of the FDD algorithms. Pure
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d65a8857efaebd1bf036c53bc57a0791
https://doi.org/10.1080/21642583.2015.1018552
https://doi.org/10.1080/21642583.2015.1018552
Autor:
Pradeep Kumar Biswal, Santosh Biswas
Publikováno v:
MED
Now-a-days On-line testing becomes an indispensable part of DFT (design for testability) for detecting rapidly increasing intermittent faults in deep sub-micron ICs. Much of the proposed on-line testing techniques are for synchronous circuits as comp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e8cbdbd914c8a7a597a90ed7fe032a45
https://doi.org/10.1109/med.2015.7158773
https://doi.org/10.1109/med.2015.7158773
Publikováno v:
VLSI Design, Vol 2015 (2015)
With the increase in soft failures in deep submicron ICs, online testing is becoming an integral part of design for testability. Some techniques for online testing of asynchronous circuits are proposed in the literature, which involves development of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3ad75b36e184ef2806192805b7fe6907
https://doaj.org/article/87efeb154c3d48dc995769c067fd232d
https://doaj.org/article/87efeb154c3d48dc995769c067fd232d