Zobrazeno 1 - 10
of 103
pro vyhledávání: '"Prab Varma"'
Autor:
Prab Varma, Miroslav N. Velev
Publikováno v:
2016 IEEE International High Level Design Validation and Test Workshop (HLDVT).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5c4f044d345e7e5ee9e7443fb51a4eeb
https://doi.org/10.1109/hldvt.2016.7748242
https://doi.org/10.1109/hldvt.2016.7748242
Autor:
Prab Varma
Publikováno v:
Asian Test Symposium
An overview of test generation approaches to maximize power supply noise is provided and issues related to and research directions for generation of test vectors with representative power are discussed. In particular, to facilitate the early design a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::04424caef77142415bb2fbe25d05d08c
https://doi.org/10.1109/ats.2012.68
https://doi.org/10.1109/ats.2012.68
Publikováno v:
2012 IEEE 30th VLSI Test Symposium (VTS).
Each year, VTS proudly presents the Best Paper Award to the author(s) of the most outstanding paper from those presented at the previous year's symposium. The candidates for this honor are initially selected based solely on the numerical ratings of t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e01d14a80daf2c5263f5894840b83944
https://doi.org/10.1109/vts.2012.6231109
https://doi.org/10.1109/vts.2012.6231109
Autor:
Tushar Gheewala, Prab Varma
Publikováno v:
Journal of Electronic Testing. 5:179-193
In this article, scan design for testability (DFT) methods are categorized based on the percentage of storage elements made scannable. The non-scan element state retention problem that occurs in partial scan design methods, in which not all of the st
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::edee4832c76c8a0865de3194942fd539
https://doi.org/10.1007/bf00972078
https://doi.org/10.1007/bf00972078
Autor:
Prab Varma
Publikováno v:
DAC
To meet the challenges involved in designing systems on silicon, IC designers are increasingly adopting a design re-use methodology, in which pre-designed logic modules, often called virtual components (VC) or intellectual property (IP) cores, are in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::89cd74f639587fd2cd2100e9e1c31bd4
https://doi.org/10.1145/277044.277232
https://doi.org/10.1145/277044.277232
Autor:
Prab Varma, Tushar Gheewala
Publikováno v:
Economics of Electronic Design, Manufacture and Test ISBN: 9781441951427
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::82d855a9139237088b9f23f836323f4b
https://doi.org/10.1007/978-1-4757-5048-5_5
https://doi.org/10.1007/978-1-4757-5048-5_5
Publikováno v:
2012 IEEE International High Level Design Validation & Test Workshop (HLDVT); 1/ 1/2012, p1-1, 1p
Publikováno v:
2008 IEEE International High Level Design Validation & Test Workshop; 2008, piv-iv, 1p
Conference
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.