Zobrazeno 1 - 10
of 57
pro vyhledávání: '"Podpod, A."'
Autor:
Inoue, Fumihiro *, Podpod, Arnita, Peng, Lan, Phommahaxay, Alain, Rebibis, Kenneth June, Uedono, Akira, Beyne, Eric
Publikováno v:
In Journal of Manufacturing Processes October 2020 58:811-818
Publikováno v:
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).
Autor:
Fumihiro Inoue, Lan Peng, Alain Phommahaxay, Kenneth June Rebibis, Arnita Podpod, Eric Beyne, Akira Uedono
Publikováno v:
Journal of Manufacturing Processes. 58:811-818
Direct wafer bonding is getting a standard and essential process in high density 3D integration devices. In this study, we investigated impact of direct bonding interface and extremely thinned Si on dicing and thinning processes. By comparing single
Publikováno v:
2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC).
Fan-Out Wafer-Level-Packaging (FOWLP) has an increased interest because of its lower cost substrate-less and lower footprint driven by the need for higher-density, higher-bandwidth chip-to-chip connections. However, FOWLP process is facing many chall
Autor:
Kennes Koen, Beyne Eric, Bertheau Julien, Duval Fabrice F.C, Phommahaxay Alain, Miller Andy, Beyer Gerald, Bex Pieter, Podpod Arnita, Kubota Tadashi
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
The present study deals with the investigation of compression mold processes and materials to enable a highdensity chip-first multi-die Fan-Out assembly. Wafer warpage, die shift and mold filling are investigated on 300mm wafers using various Epoxy M
Autor:
Andy Miller, Walter Spiess, John Slabbekoorn, Arnita Podpod, Inge Asselberghs, Stefan Lutter, Kim Yess, Erik Sleeckx, Koen Kennes, Luke Prenger, Alice Guerrero, Iuliana Radu, Sebastian Tussing, Steven Brems, Cedric Huyghebaert, Gerald Beyer, Alain Phommahaxay, Thomas Rapps, Kim Arnold, Eric Beyne
Publikováno v:
2019 International Wafer Level Packaging Conference (IWLPC).
Thin substrate handling has become one of the cornerstone technologies that enabled the development of 3D stacked ICs over the past years. Temporary wafer bonding has continuously improved and reached the maturity level required by volume manufacturi
Autor:
Alice Guerrero, Tom Cochet, Arnita Podpod, Hariharan Arumugam, Koen Kennes, Qi Wu, Kim Yess, Erick Sleeckx, Kim Arnold, Julien Bertheau, Andy Miller, Gerald Beyer, Eric Beyne, Alain Phommahaxay, Pieter Bex, Kenneth June Rebibis, Xiao Liu
Publikováno v:
2019 International Wafer Level Packaging Conference (IWLPC).
Next-generation temporary bonding adhesive material is introduced into imec's high interconnect density flip chip on fan-out wafer-level package (FC FOWLP) concept [1], [2]. After molding on silicon substrates, an ultralow die shift with an average o
Autor:
Erik Sleeckx, Andy Miller, Pieter Bex, Arnita Podpod, Alain Phommahaxay, Alice Guerrero, John Slabbekoorn, Kim Yess, Abdellah Salahoueldhadj, Kim Arnold, Eric Beyne, G. Beyer, Julien Bertheau
Publikováno v:
2019 IEEE 69th Electronic Components and Technology Conference (ECTC).
As the need for higher degrees of function integration on chips continues to rise, chip-to-chip connection density exponentially increases. The continuous push for denser interconnects has brought conventional FO-WLP to its limit. A novel FO-WLP conc
Autor:
Samuel Suhard, Fumihiro Inoue, Hitoshi Hoshino, Alain Phommahaxay, Eric Beyne, Andy Miller, Kenneth June Rebibis, Berthold Moeller, Arnita Podpod, Erik Sleeckx
Publikováno v:
2019 IEEE 69th Electronic Components and Technology Conference (ECTC).
Feasibility study of alternative dicing technologies for collective die to wafer direct bonding combined with wafer to wafer direct bonded dies has been performed. Several dicing technologies such as blade dicing, laser grooving + plasma dicing, lase
Autor:
Alain Phommahaxay, Kenneth June Rebibis, Eric Beyne, Abdellah Salahouelhadj, Arnita Podpod, Mireia Bargallo Gonzalez, Kris Vanstreels
Publikováno v:
2019 20th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE).
Wafer warpage is a big challenge during wafer process in Fan-Out Wafer-Level-Packaging (FOWLP). It is crucial to keep warpage low as much as possible for successful process integration. The warpage is mainly due to the Coefficient of Thermal Expansio