Zobrazeno 1 - 10
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pro vyhledávání: '"Po-Yen Chiu"'
Autor:
Po-Yen Chiu, 邱柏硯
電機學院IC設計產業專班
96
The aim in this thesis is to design the low-leakage power-rail ESD clamp in nanoscale CMOS technology. The principles are using circuit and component characteristics to minimize leakage of the circuit. Be
96
The aim in this thesis is to design the low-leakage power-rail ESD clamp in nanoscale CMOS technology. The principles are using circuit and component characteristics to minimize leakage of the circuit. Be
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/66617011935518793997
Publikováno v:
Pharmacognosy Magazine. 19:295-302
Background Cisplatin, the first-line drug for chemotherapy, often has limited treatment efficacy because of resistance and cancer recurrence mechanisms. Tetrandrine is a unique secondary metabolite of Stephania tetrandra. As a traditional Chinese med
Publikováno v:
Emirates Journal of Food & Agriculture (EJFA); 2023, Vol. 35 Issue 12, p1-8, 8p
Publikováno v:
The Journal of veterinary medical science. 84(8)
Corni fructus is consumed as food and herbal medicine in Chinese culture. Studies have revealed that corni fructus exhibits potent antioxidant activity; however, few studies have investigated the ability of corni fructus to lower uric acid concentrat
Publikováno v:
IEEE Transactions on Electron Devices. 64:642-645
Due to the snapback holding voltage of high-voltage (HV) nMOS smaller than the maximum operating voltage, the traditional power-rail electrostatic discharge (ESD) clamp circuit implemented with such HV nMOS suffered latchup-like failure in a touch pa
Autor:
Ming-Dou Ker, Po Yen Chiu
Publikováno v:
Microelectronics Reliability. 54:64-70
Between the metal–insulator–metal (MIM) capacitor and metal–oxide–metal (MOM) capacitor, the MIM capacitor has a better characteristic of stable capacitance. However, the MOM capacitors can be easily realized through the metal interconnection
Autor:
Ming-Dou Ker, Po-Yen Chiu
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 60:2549-2560
A new 2×VDD-tolerant input/output (I/O) buffer with process, voltage, and temperature (PVT) compensation is proposed and verified in a 90-nm CMOS process. Consisting of the dynamic source bias and gate controlled technique, the proposed mixed-voltag
Autor:
Ming-Dou Ker, Po-Yen Chiu
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 11:474-483
A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with consideration of the gate leakage issue has been proposed and verified in a 65-nm low-voltage CMOS process. Consisting of the new low-leakage ESD-detection circuit
Autor:
Po Yen Chiu, 邱博雁
102
Cloud parallel computing is several times faster than traditional stand-alone equipment. Cloud means network, and parallel computing is to increase the number of operations by tandem computers and thus to accelerate computing. Cloud computin
Cloud parallel computing is several times faster than traditional stand-alone equipment. Cloud means network, and parallel computing is to increase the number of operations by tandem computers and thus to accelerate computing. Cloud computin
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/4446mq
Autor:
Po-Yen Chiu, Ming-Dou Ker
Publikováno v:
SoCC
The novel 2×VDD NOT, NAND, and NOR logic gates have been designed and implemented in a nanoscale CMOS process with only 1×VDD devices. With the proposed dynamic source bias technique, the logic gates can be designed to have 2×VDD tolerant capabili